Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48232 )
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
soc/mediatek/mt8183: Add DRAM_DMA section
mtlib_load_and_run uses DRAM_DMA section as CBFS buffer. The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted for using mtlib_load_and_run. Unless this section is used by the DMA hardware, it is not necessary to be marked as non-cacheable resource.
Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633 Signed-off-by: Yidi Lin yidi.lin@mediatek.com --- A src/soc/mediatek/mt8183/include/soc/symbols.h M src/soc/mediatek/mt8183/memlayout.ld 2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/48232/1
diff --git a/src/soc/mediatek/mt8183/include/soc/symbols.h b/src/soc/mediatek/mt8183/include/soc/symbols.h new file mode 100644 index 0000000..2c281b4 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/symbols.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MEDIATEK_MT8183_SYMBOLS_H_ +#define _SOC_MEDIATEK_MT8183_SYMBOLS_H_ +#include <symbols.h> + +DECLARE_REGION(dram_dma) + +#endif /* _SOC_MEDIATEK_MT8183_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld index a266377..6a6b5b2 100644 --- a/src/soc/mediatek/mt8183/memlayout.ld +++ b/src/soc/mediatek/mt8183/memlayout.ld @@ -14,6 +14,11 @@ #define DRAM_INIT_CODE(addr, size) \ REGION(dram_init_code, addr, size, 4)
+#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + SECTIONS { SRAM_START(0x00100000) @@ -36,7 +41,8 @@ SRAM_L2C_END(0x00280000)
DRAM_START(0x40000000) - POSTRAM_CBFS_CACHE(0x40000000, 2M) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 1M) RAMSTAGE(0x40200000, 256K)
BL31(0x54600000, 0x60000)
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48232 )
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48232/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48232/1//COMMIT_MSG@12 PS1, Line 12: Unless this section is used by the DMA hardware, it is not necessary Either start a new paragraph, or move some words to the previous line.
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48232
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
soc/mediatek/mt8183: Add DRAM_DMA section
mtlib_load_and_run uses DRAM_DMA section as CBFS buffer. The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted for using mtlib_load_and_run.
On mt8173 and mt8192, this region is used by DMA hardware and is marked as non-cacheable resource. On mt8183, this region is reserved as CBFS buffer. This region is not necessary to be marked as non-cacheable resource.
Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633 Signed-off-by: Yidi Lin yidi.lin@mediatek.com --- A src/soc/mediatek/mt8183/include/soc/symbols.h M src/soc/mediatek/mt8183/memlayout.ld 2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/48232/2
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48232 )
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48232/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48232/1//COMMIT_MSG@12 PS1, Line 12: Unless this section is used by the DMA hardware, it is not necessary
Either start a new paragraph, or move some words to the previous line.
Done
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48232
to look at the new patch set (#3).
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
soc/mediatek/mt8183: Add DRAM_DMA section
mtlib_init_mcu uses DRAM_DMA section as CBFS buffer. The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted for using mtlib_init_mcu.
On mt8173 and mt8192, this region is used by DMA hardware and is marked as non-cacheable resource. On mt8183, this region is reserved as CBFS buffer. This region is not necessary to be marked as non-cacheable resource.
Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633 Signed-off-by: Yidi Lin yidi.lin@mediatek.com --- A src/soc/mediatek/mt8183/include/soc/symbols.h M src/soc/mediatek/mt8183/memlayout.ld 2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/48232/3
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48232 )
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48232/3/src/soc/mediatek/mt8183/mem... File src/soc/mediatek/mt8183/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/48232/3/src/soc/mediatek/mt8183/mem... PS3, Line 46: POSTRAM_CBFS_CACHE(0x40100000, 1M) I'm not sure if 1M is too small for CBFS cache. What about moving RAMSTAGE to 0x40300000 ?
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48232 )
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/48232/3/src/soc/mediatek/mt8183/mem... File src/soc/mediatek/mt8183/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/48232/3/src/soc/mediatek/mt8183/mem... PS3, Line 46: POSTRAM_CBFS_CACHE(0x40100000, 1M)
I'm not sure if 1M is too small for CBFS cache. […]
oh never mind - ignore my comment.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48232 )
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48232/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48232/4//COMMIT_MSG@15 PS4, Line 15: . This region , so it
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48232
to look at the new patch set (#5).
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
soc/mediatek/mt8183: Add DRAM_DMA section
mtlib_init_mcu uses DRAM_DMA section as CBFS buffer. The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted for using mtlib_init_mcu.
On mt8173 and mt8192, this region is used by DMA hardware and is marked as non-cacheable resource. On mt8183, this region is reserved as CBFS buffer, it is not necessary to be marked as non-cacheable resource.
Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633 Signed-off-by: Yidi Lin yidi.lin@mediatek.com --- A src/soc/mediatek/mt8183/include/soc/symbols.h M src/soc/mediatek/mt8183/memlayout.ld 2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/48232/5
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48232 )
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48232/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48232/4//COMMIT_MSG@15 PS4, Line 15: . This region
, so it
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48232 )
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48232/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48232/5//COMMIT_MSG@15 PS5, Line 15: it Either "so it" or "and"
Hello Hung-Te Lin, build bot (Jenkins), Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48232
to look at the new patch set (#6).
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
soc/mediatek/mt8183: Add DRAM_DMA section
mtk_init_mcu uses DRAM_DMA section as CBFS buffer. The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted for using mtk_init_mcu.
On mt8173 and mt8192, this region is used by DMA hardware and is marked as non-cacheable resource. On mt8183, this region is reserved as CBFS buffer, so it is not necessary to be marked as non-cacheable resource.
Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633 Signed-off-by: Yidi Lin yidi.lin@mediatek.com --- A src/soc/mediatek/mt8183/include/soc/symbols.h M src/soc/mediatek/mt8183/memlayout.ld 2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/48232/6
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48232 )
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48232/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48232/5//COMMIT_MSG@15 PS5, Line 15: it
Either "so it" or "and"
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48232 )
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
Patch Set 6: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48232 )
Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ......................................................................
soc/mediatek/mt8183: Add DRAM_DMA section
mtk_init_mcu uses DRAM_DMA section as CBFS buffer. The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted for using mtk_init_mcu.
On mt8173 and mt8192, this region is used by DMA hardware and is marked as non-cacheable resource. On mt8183, this region is reserved as CBFS buffer, so it is not necessary to be marked as non-cacheable resource.
Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633 Signed-off-by: Yidi Lin yidi.lin@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48232 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org --- A src/soc/mediatek/mt8183/include/soc/symbols.h M src/soc/mediatek/mt8183/memlayout.ld 2 files changed, 16 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8183/include/soc/symbols.h b/src/soc/mediatek/mt8183/include/soc/symbols.h new file mode 100644 index 0000000..2c281b4 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/symbols.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MEDIATEK_MT8183_SYMBOLS_H_ +#define _SOC_MEDIATEK_MT8183_SYMBOLS_H_ +#include <symbols.h> + +DECLARE_REGION(dram_dma) + +#endif /* _SOC_MEDIATEK_MT8183_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld index db56666..a549274 100644 --- a/src/soc/mediatek/mt8183/memlayout.ld +++ b/src/soc/mediatek/mt8183/memlayout.ld @@ -14,6 +14,11 @@ #define DRAM_INIT_CODE(addr, size) \ REGION(dram_init_code, addr, size, 4)
+#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + SECTIONS { SRAM_START(0x00100000) @@ -37,7 +42,8 @@ SRAM_L2C_END(0x00280000)
DRAM_START(0x40000000) - POSTRAM_CBFS_CACHE(0x40000000, 2M) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 1M) RAMSTAGE(0x40200000, 256K)
BL31(0x54600000, 0x60000)
-
Hung-Te Lin (Code Review) -
Yidi Lin (Code Review)
-
Yu-Ping Wu (Code Review)