Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin.
Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )
Change subject: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes ......................................................................
Patch Set 19:
(9 comments)
Patchset:
PS6:
According to the SIO datasheet I could temporarily change RSTOUT2# to GP76 using config register 0x2 […]
Done
Patchset:
PS7:
Guys, as I wrote on the mailing list, I am getting real close to actually implement the whole thing. […]
Done
PS7:
I place the JMicron card reader in PCIEX16_3, to prevent pcie_port_coalesce being enabled at runtime […]
Done
File src/mainboard/asus/p8x7x-series/mainboard.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/c9cc7ea5_8dba36ad?usp... : PS14, Line 67: if (me_sig != -1 &&
Yes. […]
Patchset 19 with an intact ME can program IFD well on my p8z77-v now, even with x4. The only regression is that the PCI product ID of the IGD is changed to 0xffff, making the IGD effectively disabled, possibly by ME.
With a neutralized and disabled ME, Patchset 19 seems works fine, with IGD available.
File src/mainboard/asus/p8x7x-series/pcielane.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/d3773ca4_3955a18a?usp... : PS10, Line 97: /* Verify */
Please use rdev_readat(), rdev_eraseat() and rdev_writeat() to access SPI flash as in patchset 13, r […]
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/978e8e6e_32bc435b?usp... : PS1, Line 67: gpio5 |= 0x20;
PCHSTRP9 : 0x30004d80, I also have another three descriptors with PCHSTRP9 0x30004d81, 0x30004d82, […]
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/4bc3d6ab_d34825d2?usp... : PS2, Line 77: {7, 34, 20, -1}
Fix in. Thanks for the catch. […]
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/99b7a19a_2915504f?usp... : PS7, Line 104: 0x40
Probably the same issue. […]
Done
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/pcielane.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/3caee449_f20f3352?usp... : PS8, Line 131: gpio5 = 0x20;
How many times did the board power cycle between your changing […]
Done
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Bill XIE (Code Review)