Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 )
Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ......................................................................
Patch Set 81:
(26 comments)
https://review.coreboot.org/c/coreboot/+/32734/74/Documentation/mainboard/su... File Documentation/mainboard/supermicro/x11ssh-tf.md:
https://review.coreboot.org/c/coreboot/+/32734/74/Documentation/mainboard/su... PS74, Line 30: S5 resume
We will do it in a follow-up.
Done
https://review.coreboot.org/c/coreboot/+/32734/74/Documentation/mainboard/su... PS74, Line 37: 10GB
Done
Done
https://review.coreboot.org/c/coreboot/+/32734/74/Documentation/mainboard/su... File Documentation/mainboard/supermicro/x11ssh_flash.jpg:
PS74:
We will do it in a follow-up.
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11ssh/Kconfig:
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 9: select MAINBOARD_USES_FSP2_0
Done
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 18: config SOC_INTEL_COMMON_BLOCK_SGX
Done
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 67: : config SUBSYSTEM_VENDOR_ID : hex : default 0x8086
Yes, in `soc/intel/skylake/chip_fsp20. […]
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 76: endif
Done
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11ssh/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 1: BOARD_SUPERMICRO_X11SSH_PLUS_TF : bool "X11SSH+-TF"
We will do it in a follow-up.
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11ssh/board_info.txt:
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 5: ROM socketed: n
They aren't.
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11ssh/bootblock.c:
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 37: garbeled
We will do it in a follow-up.
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11ssh/mainboard.c:
PS74:
Done
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11ssh/ramstage.c:
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 3: *
Copyright holders will be transferred to AUTHORS file soon.
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11ssh/romstage.c:
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 3: *
Same.
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt:
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 5: ROM socketed: n
The retail ones are, so you don't have a retail board, right?
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 30: "Device4Enable" = "1"
Done
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 73: register "SsicPortEnable" = "0"
No.
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 114: X550T
Done
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 203: device domain 0 on
Maybe add a 'subsystemid 0x1234 0x5678 inherit' line right after this line ('device domain 0 on') […]
We will do it in a follow-up.
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 205: unused
Looks like it's routed to the LSI SAS3008 (only on the X11SSH-CTF, unpopulated on the X11SSH-TF).
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 208: JPCIE1
SLOT6 […]
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 216: JPCIE1
SLOT4
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 219: device pci 00.0 on end # Aspeed 2400 VGA
Mind elaborating a bit as to why? I am quite intrigued by it.
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 223: 10GBE
Done
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 239: device pnp 2e.0 off end
Done
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 263: device pnp 2e.b on # SUART3
I guess one could try "listening" to that virtual UART and hope something will appear. […]
Done
https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/x... PS74, Line 267: device pnp 2e.c on # SUART4
Same.
Done
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Philipp Deppenwiese (Code Review)