Change in coreboot[master]: nb/intel/haswell: Move PEG registers to a separate header

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51891 )

Change subject: nb/intel/haswell: Move PEG registers to a separate header
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nb/intel/haswell: Move PEG registers to a separate header

To keep the "main" haswell.h header short and simple, move PEG register
definitions into a separate file, as done with most other registers.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ibfca00456115a4a0c861dd6738605214a7d43fd9
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51891
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/northbridge/intel/haswell/haswell.h
A src/northbridge/intel/haswell/registers/pcie_graphics.h
2 files changed, 35 insertions(+), 29 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 6faf787..1b29f6b 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -11,39 +11,11 @@
 #include "registers/epbar.h"
 #include "registers/host_bridge.h"
 #include "registers/mchbar.h"
+#include "registers/pcie_graphics.h"

/* Device 0:0.0 PCI configuration space (Host Bridge) */
 #define HOST_BRIDGE	PCI_DEV(0, 0, 0)

-/* Device 0:1.0 PCI configuration space (PCIe Graphics) */
-
-#define PEG_CAP		0xa2
-#define PEG_DCAP	0xa4
-
-#define PEG_LCAP	0xac
-
-#define PEG_DSTS	0xaa
-
-#define PEG_SLOTCAP	0xb4
-
-#define PEG_DCAP2	0xc4	/* 32bit */
-
-#define PEG_LCTL2	0xd0
-
-#define PEG_VC0RCTL	0x114
-
-#define PEG_ESD		0x144	/* 32bit */
-#define PEG_LE1D	0x150	/* 32bit */
-#define PEG_LE1A	0x158	/* 64bit */
-
-#define PEG_UESTS	0x1c4
-#define PEG_UESEV	0x1cc
-#define PEG_CESTS	0x1d0
-
-#define PEG_L0SLAT	0x22c
-
-#define PEG_AFE_PM_TMR	0xc28
-
 /* Device 0:2.0 PCI configuration space (Graphics Device) */

#define MSAC		0x62	/* Multi Size Aperture Control */
diff --git a/src/northbridge/intel/haswell/registers/pcie_graphics.h b/src/northbridge/intel/haswell/registers/pcie_graphics.h
new file mode 100644
index 0000000..3662765
--- /dev/null
+++ b/src/northbridge/intel/haswell/registers/pcie_graphics.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef HASWELL_REGISTERS_PCIE_GRAPHICS_H
+#define HASWELL_REGISTERS_PCIE_GRAPHICS_H
+
+/* Device 0:1.0 PCI configuration space (PCIe Graphics) */
+#define PEG_CAP		0xa2
+#define PEG_DCAP	0xa4
+
+#define PEG_LCAP	0xac
+
+#define PEG_DSTS	0xaa
+
+#define PEG_SLOTCAP	0xb4
+
+#define PEG_DCAP2	0xc4	/* 32bit */
+
+#define PEG_LCTL2	0xd0
+
+#define PEG_VC0RCTL	0x114
+
+#define PEG_ESD		0x144	/* 32bit */
+#define PEG_LE1D	0x150	/* 32bit */
+#define PEG_LE1A	0x158	/* 64bit */
+
+#define PEG_UESTS	0x1c4
+#define PEG_UESEV	0x1cc
+#define PEG_CESTS	0x1d0
+
+#define PEG_L0SLAT	0x22c
+
+#define PEG_AFE_PM_TMR	0xc28
+
+#endif /* HASWELL_REGISTERS_PCIE_GRAPHICS_H */