Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39844 )
Change subject: mb/tglrvp: Add GPE configuration ......................................................................
mb/tglrvp: Add GPE configuration
Update the GPE configuration for dw0, dw1 and dw2.
Change-Id: I8b406bcbd710e84cec91a8c2d1557902e929f7cc Signed-off-by: Shaunak Saha shaunak.saha@intel.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/39844/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 23737c3..8fd9087 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -4,6 +4,14 @@ device lapic 0 on end end
+ # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index f2e5510..4ff35cc 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -4,6 +4,14 @@ device lapic 0 on end end
+ # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1"
Hello build bot (Jenkins), Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39844
to look at the new patch set (#2).
Change subject: mb/tglrvp: Add GPE configuration ......................................................................
mb/tglrvp: Add GPE configuration
Update the GPE configuration for dw0, dw1 and dw2.
BUG=None TEST=build and boot tglrvp
Change-Id: I8b406bcbd710e84cec91a8c2d1557902e929f7cc Signed-off-by: Shaunak Saha shaunak.saha@intel.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/39844/2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39844 )
Change subject: mb/tglrvp: Add GPE configuration ......................................................................
Patch Set 2: Code-Review+2
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39844 )
Change subject: mb/tglrvp: Add GPE configuration ......................................................................
Patch Set 2: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39844 )
Change subject: mb/tglrvp: Add GPE configuration ......................................................................
Patch Set 2: Code-Review+2
Can you add topic?
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39844 )
Change subject: mb/tglrvp: Add GPE configuration ......................................................................
mb/tglrvp: Add GPE configuration
Update the GPE configuration for dw0, dw1 and dw2.
BUG=None TEST=build and boot tglrvp
Change-Id: I8b406bcbd710e84cec91a8c2d1557902e929f7cc Signed-off-by: Shaunak Saha shaunak.saha@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39844 Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 16 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Srinidhi N Kaushik: Looks good to me, approved Caveh Jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 23737c3..8fd9087 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -4,6 +4,14 @@ device lapic 0 on end end
+ # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index f2e5510..4ff35cc 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -4,6 +4,14 @@ device lapic 0 on end end
+ # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1"
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Caveh Jalali (Code Review) -
Patrick Georgi (Code Review)
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Shaunak Saha (Code Review)
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Srinidhi N Kaushik (Code Review)
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Wonkyu Kim (Code Review)