[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra

[Jarried Lin (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin.

Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86027?usp=email

to look at the new patch set (#2).

Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
......................................................................

soc/mediatek/mt8196: Add GCE ddren sel control to mminfra

MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction
ACK from SPM: 0, non-SPM: 0x1.

In MT8196, SPM has masked all the DDR request, so this setting should
be set to non-SPM whenever mminfra power on every time.
Otherwise, GCE will hang when accessing DRAM.

BUG=b:379039600
TEST=boot up ok, GCE can access DRAM countinuosly

Change-Id: I30309b0426f803e28858eb15652a649927f94c7e
Signed-off-by: Jason-jh Lin 
---
M src/soc/mediatek/mt8196/include/soc/mminfra.h
M src/soc/mediatek/mt8196/mminfra.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/86027/2