Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41013 )
Change subject: soc/intel/tigerlake: Select CONFIG_TCSS_PCIE_SEGMENT for TGL ......................................................................
soc/intel/tigerlake: Select CONFIG_TCSS_PCIE_SEGMENT for TGL
This patch performs below operations 1. Include additional PCI segment by selecting TCSS_PCIE_SEGMENT from SoC 2. Clean up TGL SoC IRQ programming as TBT related programming is now moved into common code (src/soc/intel/common/block/acpi/acpi/pcisegment.asl)
Change-Id: Ib94396bd2a06b661d4828357d7a4be973846c707 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/pci_irqs.asl M src/soc/intel/tigerlake/include/soc/irq.h 3 files changed, 1 insertion(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/41013/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a690acf..93f12f9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -60,6 +60,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select TCSS_PCIE_SEGMENT
config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 62520b1..7603362 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -73,11 +73,6 @@ Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, /* D8: GNA */ Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, /* D6: PEG60 */ Package(){0x0006FFFF, 0, 0, PEG_IRQ }, /* D5: IPU Device */ @@ -142,11 +137,6 @@ Package(){0x000DFFFF, 1, 0, 10 }, /* D8: GNA */ Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, /* D6: PEG60 */ Package(){0x0006FFFF, 0, 0, 11 }, /* D5: IPU Device */ diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 01ee10b..1057f91 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -54,11 +54,6 @@
#define ISH_IRQ 16
-#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - #define HECI_1_IRQ 16 #define HECI_2_IRQ 17 #define HECI_3_IRQ 16
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41013 )
Change subject: soc/intel/tigerlake: Select CONFIG_TCSS_PCIE_SEGMENT for TGL ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41013 )
Change subject: soc/intel/tigerlake: Select CONFIG_TCSS_PCIE_SEGMENT for TGL ......................................................................
Patch Set 5:
a
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41013 )
Change subject: soc/intel/tigerlake: Select CONFIG_TCSS_PCIE_SEGMENT for TGL ......................................................................
Patch Set 5: Code-Review+1
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41013?usp=email )
Change subject: soc/intel/tigerlake: Select CONFIG_TCSS_PCIE_SEGMENT for TGL ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.