Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Upgrade UART GPIO programming

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25192

Change subject: soc/amd/stoneyridge/southbridge.c: Upgrade UART GPIO programming
......................................................................

soc/amd/stoneyridge/southbridge.c: Upgrade UART GPIO programming

Procedure configure_stoneyridge_uart() uses direct GPIO mux programming.
Replace old style direct mux GPIO programming with a GPIO table and a call
to centralized GPIO programming.

BUG=b:74258015
TEST=Build and boot kahlee, observing serial output does not changes from
previous serial output.

Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98
Signed-off-by: Richard Spiegel 
---
M src/soc/amd/stoneyridge/southbridge.c
1 file changed, 8 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/25192/1

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index a41ad1b..cce87e3 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -331,13 +331,17 @@
    } while (!status);
 }

+const static struct soc_amd_stoneyridge_gpio uart_gpio[] = {
+	PAD_NF(GPIO_137, UART0_RTS_L, PULL_NONE),
+	PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
+	PAD_NF(GPIO_142, UART1_RTS_L, PULL_NONE),
+	PAD_NF(GPIO_143, UART1_TXD, PULL_NONE)
+};
+
 void configure_stoneyridge_uart(void)
 {
    /* Set the GPIO mux to UART */
-	write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);
-	write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);
-	write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0);
-	write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0);
+	sb_program_gpios(uart_gpio, ARRAY_SIZE(uart_gpio));
 }

void sb_pci_port80(void)