Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56007 )
Change subject: soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine ......................................................................
soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore switch tigerlake boards to this method.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5 --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/southbridge.asl M src/soc/intel/tigerlake/pmc.c 3 files changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/56007/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index e41d7a7..520b7f2 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -47,6 +47,8 @@ select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 59bcf74..8300c23 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -38,8 +38,5 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>
-/* Intel Power Engine Plug-in */ -#include <soc/intel/common/block/acpi/acpi/pep.asl> - /* GbE 0:1f.6 */ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl> diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index dd2b61b..10ba110 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -11,6 +11,7 @@ #include <device/mmio.h> #include <device/device.h> #include <drivers/intel/pmc_mux/chip.h> +#include <intelblocks/acpi.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/pmc_ipc.h> @@ -121,6 +122,8 @@ acpigen_pop_len(); /* PMC Device */ acpigen_pop_len(); /* Scope */
+ generate_acpi_power_engine(); + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, dev_path(dev)); }