Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37902 )
Change subject: mb/google/celes: Add missing devicetree USB settings ......................................................................
mb/google/celes: Add missing devicetree USB settings
Chromium commit ebff567 [Celes: Adopt USB related change from strago] adapted the Brasell D0 stepping USB changes from Strago-based boards, but the devicetree additions were missed when upstreaming. Add them.
Change-Id: If5f330bbefe7fb9cb21d7a08721094f52a180e33 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/google/cyan/variants/celes/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/37902/1
diff --git a/src/mainboard/google/cyan/variants/celes/devicetree.cb b/src/mainboard/google/cyan/variants/celes/devicetree.cb index a1ab510..2e708af 100644 --- a/src/mainboard/google/cyan/variants/celes/devicetree.cb +++ b/src/mainboard/google/cyan/variants/celes/devicetree.cb @@ -73,6 +73,12 @@ register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" register "PcdSdDetectChk" = "0" # Disable SD card detect + # Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength) + register "D0Usb2Port0PerPortRXISet" = "2" + register "D0Usb2Port1PerPortRXISet" = "2" + register "D0Usb2Port2PerPortRXISet" = "2" + register "D0Usb2Port3PerPortRXISet" = "2" + register "D0Usb2Port4PerPortRXISet" = "2"
# LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
Matt DeVillier has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37902 )
Change subject: mb/google/celes: Add missing devicetree USB settings ......................................................................
Abandoned
forgot this was moved to ramstage override
-
Matt DeVillier (Code Review)