Change in coreboot[master]: mb/google/brya/variants/brask: Disable autonomous GPIO power management

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60100 )

Change subject: mb/google/brya/variants/brask: Disable autonomous GPIO power management
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mb/google/brya/variants/brask: Disable autonomous GPIO power management

We experienced the `Cr50 i2c TPM IRQ timeout!` error when the device
executed the reboot test even though we have updated the Cr50 firmware
to the latest version 0.6.70. Besides, we also experienced the device
failed with the IRQ timeout when using the 0.3.22 Cr50 firmware in the
factory. In order to fix these issues, we disable the gpio power
management from the devicetree.

BUG=b:210540890
TEST=reboot 100 cycles without the error message.

Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5
Signed-off-by: Zhuohao Lee 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60100
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Paul Menzel 
---
M src/mainboard/google/brya/variants/brask/overridetree.cb
1 file changed, 10 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb
index 63a683d..a7b763f 100644
--- a/src/mainboard/google/brya/variants/brask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brask/overridetree.cb
@@ -1,4 +1,14 @@
 chip soc/intel/alderlake
+	# This disables autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
    device domain 0 on
    	device ref dtt on
    		chip drivers/intel/dptf