[S] Change in coreboot[main]: mb/hp/elitebook_820_g2: Add HP Sure Start workaround

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79881?usp=email )

Change subject: mb/hp/elitebook_820_g2: Add HP Sure Start workaround
......................................................................

mb/hp/elitebook_820_g2: Add HP Sure Start workaround

To work around HP Sure Start the top of flash needs to contain a vendor
provided image that the EC verifies before releasing the X86 from reset.

Instead of using the wrong flash size and padding the image with dd, add
an fmap layout and use cbfstool memory map arguments to achieve the
same.

UNTESTED.

Signed-off-by: Arthur Heymans 
Change-Id: I0e59d035ce9281062272aeef92f50f2bbf3a9c5f
---
M Documentation/mainboard/hp/elitebook_820_g2.md
M src/mainboard/hp/elitebook_820_g2/Kconfig
M src/mainboard/hp/elitebook_820_g2/Makefile.inc
A src/mainboard/hp/elitebook_820_g2/board.fmd
4 files changed, 42 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/79881/1

diff --git a/Documentation/mainboard/hp/elitebook_820_g2.md b/Documentation/mainboard/hp/elitebook_820_g2.md
index 5d35c30..d136f4d 100644
--- a/Documentation/mainboard/hp/elitebook_820_g2.md
+++ b/Documentation/mainboard/hp/elitebook_820_g2.md
@@ -74,13 +74,12 @@

flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new

-Then flash the coreboot image:
+Then flash the coreboot image, while making sure CONFIG_HP_SURE_START_WORKAROUND_LAYOUT is set:

-    # first extend the 12M coreboot.rom to 16M
-    fallocate -l 16M build/coreboot.rom
     flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom

-After coreboot is installed, the coreboot firmware can be updated with internal flashing:
+After coreboot is installed, the coreboot firmware can be updated with internal flashing by
+by only flashing the BIOS region:

flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom

diff --git a/src/mainboard/hp/elitebook_820_g2/Kconfig b/src/mainboard/hp/elitebook_820_g2/Kconfig
index 98aed5c..0bfec31 100644
--- a/src/mainboard/hp/elitebook_820_g2/Kconfig
+++ b/src/mainboard/hp/elitebook_820_g2/Kconfig
@@ -4,7 +4,7 @@

config BOARD_SPECIFIC_OPTIONS
    def_bool y
-	select BOARD_ROMSIZE_KB_12288
+	select BOARD_ROMSIZE_KB_16384
    select EC_HP_KBC1126
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
@@ -28,4 +28,16 @@
 config EC_HP_KBC1126_GPE
    default 0x6

+config HP_SURE_START_WORKAROUND_LAYOUT
+	bool "Use a FMAP designed to work around HP Sure Start"
+	default y
+	help
+	  HP Sure start verifies the content of the flash against a signature.
+	  If a modified IFD is used to put coreboot in a different location in
+	  the flash the EC still hapilly verifies the vendor bootblock located
+	  at the end of flash but executes a coreboot bootblock.
+
+config FMDFILE
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" if HP_SURE_START_WORKAROUND_LAYOUT
+
 endif
diff --git a/src/mainboard/hp/elitebook_820_g2/Makefile.inc b/src/mainboard/hp/elitebook_820_g2/Makefile.inc
index 774dbf1..105bb8d 100644
--- a/src/mainboard/hp/elitebook_820_g2/Makefile.inc
+++ b/src/mainboard/hp/elitebook_820_g2/Makefile.inc
@@ -4,3 +4,13 @@
 romstage-y += pei_data.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 ramstage-y += pei_data.c
+
+
+ifeq ($(CONFIG_HP_SURE_START_WORKAROUND_LAYOUT),y)
+# Match this with board.fmd
+BIOS_REGION_FLASH_BASE=0x600000
+BIOS_REGION_SIZE=0x600000
+BIOS_REGION_MMAP_BASE=$(call int-subtract, 0x100000000 $(BIOS_REGION_SIZE))
+
+CBFSTOOL_ADD_CMD_OPTIONS += --mmap $(BIOS_REGION_FLASH_BASE):$(BIOS_REGION_MMAP_BASE):$(BIOS_REGION_SIZE)
+endif
diff --git a/src/mainboard/hp/elitebook_820_g2/board.fmd b/src/mainboard/hp/elitebook_820_g2/board.fmd
new file mode 100644
index 0000000..86d66be
--- /dev/null
+++ b/src/mainboard/hp/elitebook_820_g2/board.fmd
@@ -0,0 +1,16 @@
+FLASH 0x1000000 {
+	SI_ALL@0x0 0x600000 {
+		SI_DESC 0x1000
+		SI_GBE 0x2000
+		SI_ME
+	}
+	SI_BIOS@0x600000 0x600000 {
+		UNIFIED_MRC_CACHE 0x20000 {
+			RECOVERY_MRC_CACHE 0x10000
+			RW_MRC_CACHE 0x10000
+		}
+		FMAP 0x800
+		COREBOOT(CBFS)
+	}
+	SI_PD@0xEB5000 0x14B000
+}