Attention is currently required from: Arthur Heymans, Nico Huber.
Hello Arthur Heymans, Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64189?usp=email
to look at the new patch set (#7).
Change subject: haswell NRI: Add DDR3 JEDEC reset and init ......................................................................
haswell NRI: Add DDR3 JEDEC reset and init
Implement JEDEC reset and init sequence for DDR3. The MRS commands are issued through the REUT (Robust Electrical Unified Testing) hardware.
Change-Id: I2a0c066537021b587599228086727cb1e041bff5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/native_raminit/Makefile.mk A src/northbridge/intel/haswell/native_raminit/ddr3.c M src/northbridge/intel/haswell/native_raminit/io_comp_control.c A src/northbridge/intel/haswell/native_raminit/jedec_reset.c M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/raminit_native.h M src/northbridge/intel/haswell/native_raminit/reg_structs.h A src/northbridge/intel/haswell/native_raminit/reut.c M src/northbridge/intel/haswell/registers/mchbar.h M src/southbridge/intel/lynxpoint/pch.h 10 files changed, 833 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/64189/7