Change in coreboot[master]: soc/intel/common/basecode/eop: coreboot driver perform EOP operations

[Subrata Banik (Code Review)]

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 )

Change subject: soc/intel/common/basecode/eop: coreboot driver perform EOP operations
......................................................................

Patch Set 23:

(1 comment)

File src/soc/intel/common/basecode/eop/eop.c:

https://review.coreboot.org/c/coreboot/+/60405/comment/b385050a_c85635c0 
PS23, Line 20: static void do_eop_operations(void *unused)
             : {
             : 	if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
             : 		/* Step 1 */
             : 		cse_send_end_of_post();
             : 
             : 		/* Step 2 */
             : 		cse_lock_config();
             : 
             : 		/* Step 3 */
             : 		if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
             : 			cse_set_to_d0i3();
             : 			heci1_disable();
             : 		}
             : 	}
             : 
             : 	if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) {
             : 		/* Step 4 */
             : 		heci_set_to_d0i3();
             : 		/* Step 5 */
             : 		pmc_clear_pmcon_sts();
             : 	}
             : }
> For CSE and SPI, yes. I'm not sure if the PMC is handled specially, but if it's treated like a regular PCI device then we should also use its device operations.

Looking at CB:41384 from Tim, seems to me that we can add .final for PMC as well and it will perform PCI enumeration as well for hidden device like PMC.

"This allows
child devices to be enumerated correctly and also PCI resources can be
designated from the {read,set}_resources callbacks."