Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49181 )
Change subject: [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge ......................................................................
[UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge
Both ends of the DMI link must use the same TC/VC mapping. Since the register values are identical, pass the northbridge values as parameters and have the southbridge code use them. This prevents any inconsistency.
Change-Id: I598cd5b6bd1af22ee2ae25a4f29cae381116bd5d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/early_dmi.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 3 files changed, 27 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/49181/1
diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index bcf3e4c..7d536b5 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -180,26 +180,33 @@
printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); /* - * Virtual Channel resources must match settings in RCBA! - * * Channel Vp and Vm are documented in: * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium * Processor Family, and Desktop Intel Celeron Processor Family Vol. 2" */
- /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ - DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; - /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ - DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); - /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ - DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0 */ + const u32 vc0 = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + + /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1 */ + const u32 vc1 = (1 << 31) | (1 << 24) | (0x11 << 1); + + /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ + const u32 vcp = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ - DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); + const u32 vcm = (1 << 31) | (7 << 24) | (0x40 << 1); + + DMIBAR32(DMIVC0RCTL) = vc0; + DMIBAR32(DMIVC1RCTL) = vc1; + DMIBAR32(DMIVCPRCTL) = vcp; + DMIBAR32(DMIVCMRCTL) = vcm;
/* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ DMIBAR8(DMIPVCCAP1) |= 1;
- early_pch_init_native_dmi_post(); + /* Ensure the PCH side uses the same virtual channel settings */ + early_pch_init_native_dmi_post(vc0, vc1, vcp, vcm);
/* * BIOS Requirement: Check if DMI VC Negotiation was successful. diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 251ff86..eac8e1f 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -28,7 +28,7 @@ RCBA8(DLCTL2) = (RCBA8(DLCTL2) & ~0xf) | 2; }
-void early_pch_init_native_dmi_post(void) +void early_pch_init_native_dmi_post(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm) { u32 reg32;
@@ -42,47 +42,21 @@
RCBA8(UPDCR) = RCBA8(UPDCR) | 1 << 2 | 1 << 0;
- /* - * Virtual Channel resources must match settings in DMIBAR! - * - * Some of the following settings are taken from - * "Intel Core i5-600, i3-500 Desktop Processor Series and Intel - * Pentium Desktop Processor 6000 Series Vol. 2" datasheet and - * serialice traces. - */ + /* Virtual Channel 0 */ + RCBA32(V0CTL) = vc0;
- /* Virtual Channel 0 Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC0 and TC3 and TC4 to VC0. - */ - - RCBA32(V0CTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; - - /* Virtual Channel 1 Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC1 and TC5 to VC1. - */ - RCBA32(V1CTL) = (1 << 31) | (1 << 24) | (0x11 << 1); + /* Virtual Channel 1 */ + RCBA32(V1CTL) = vc1; /* Read back register */ RCBA32(V1CTL);
- /* Virtual Channel private Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC2 and TC6 to VCp. - */ - RCBA32(CIR31) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Virtual Channel private */ + RCBA32(CIR31) = vcp; /* Read back register */ RCBA32(CIR31);
- /* Virtual Channel ME Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC7 to VCm. - */ - RCBA32(CIR32) = (1 << 31) | (7 << 24) | (0x40 << 1); + /* Virtual Channel ME */ + RCBA32(CIR32) = vcm;
/* Lock Virtual Channel Resource control register. */ RCBA32(CIR0) |= TCLOCKDN; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 42c56a2..5eaaf51 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -63,7 +63,7 @@ void early_pch_init_native(void); void early_pch_init(void); void early_pch_init_native_dmi_pre(void); -void early_pch_init_native_dmi_post(void); +void early_pch_init_native_dmi_post(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm);
struct southbridge_usb_port {
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49181?usp=email )
Change subject: [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge ......................................................................
Abandoned
Angel Pons has restored this change. ( https://review.coreboot.org/c/coreboot/+/49181?usp=email )
Change subject: [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge ......................................................................
Restored
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49181?usp=email )
Change subject: [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge ......................................................................
Abandoned
No interest in pursuing this
-
Angel Pons (Code Review) -
Stefan Reinauer (Code Review)