Change in coreboot[master]: soc/intel/skylake: Auto-configure SerialIoDevMode UPD

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55224 )

Change subject: soc/intel/skylake: Auto-configure SerialIoDevMode UPD
......................................................................

soc/intel/skylake: Auto-configure SerialIoDevMode UPD

Introduce the `DERIVE_SERIALIO_CFG_FROM_DEV_STATE` Kconfig symbol, which
allows omitting the `SerialIoDevMode` setting from devicetrees where the
SerialIO settings can be derived from the PCI devices' state. Also, when
the `INTEL_LPSS_UART_FOR_CONSOLE` option is selected, configure the UART
specified by `UART_FOR_CONSOLE` to have FSP skip initialisation for it.

Also, as an example, transform hp/280_g2 to make use of this code.

Change-Id: I59ec760e4dcc6b64e40c6ebd402642070f1de33a
Signed-off-by: Angel Pons 
---
M src/mainboard/hp/280_g2/Kconfig
M src/mainboard/hp/280_g2/devicetree.cb
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/chip.c
4 files changed, 51 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/55224/1

diff --git a/src/mainboard/hp/280_g2/Kconfig b/src/mainboard/hp/280_g2/Kconfig
index 10f6828..4f18548 100644
--- a/src/mainboard/hp/280_g2/Kconfig
+++ b/src/mainboard/hp/280_g2/Kconfig
@@ -5,6 +5,7 @@
 config BOARD_SPECIFIC_OPTIONS
    def_bool y
    select BOARD_ROMSIZE_KB_8192
+	select DERIVE_SERIALIO_CFG_FROM_DEV_STATE
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
    select INTEL_GMA_HAVE_VBT
diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb
index 98fccc9..aefebf1 100644
--- a/src/mainboard/hp/280_g2/devicetree.cb
+++ b/src/mainboard/hp/280_g2/devicetree.cb
@@ -5,10 +5,6 @@
    	.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
    }"

-	register "SerialIoDevMode" = "{
-		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,	/* Routed to debug header */
-	}"
-
    register "eist_enable" = "1"

device cpu_cluster 0 on
@@ -76,7 +72,7 @@
    		}"
    		# DevSlp not supported
    	end
-		device pci 19.0 on  end		# UART #2
+		device pci 19.0 on  end		# UART #2 (routed to debug header)
    	device pci 1c.0 off end		# RP #1
    	device pci 1c.1 off end		# RP #2
    	device pci 1c.2 off end		# RP #3
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 3f02974..1fbdc39 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -177,6 +177,14 @@
    string
    default "8086,0406"

+config DERIVE_SERIALIO_CFG_FROM_DEV_STATE
+	bool
+	help
+	  Selected by mainboards where the values for the `SerialIoDevMode` FSP
+	  UPD can be derived from the PCI devices' state in the devicetree, and
+	  the INTEL_LPSS_UART_FOR_CONSOLE and UART_FOR_CONSOLE Kconfig settings.
+	  When enabled, the `SerialIoDevMode` setting in chip config is useless.
+
 config SKYLAKE_SOC_PCH_H
    bool
    default n
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index d4e8341..48b9c0b 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <assert.h>
 #include <bootsplash.h>
 #include <cbmem.h>
 #include <fsp/api.h>
@@ -220,6 +221,40 @@
    .init		= &soc_init_pre_device,
 };

+static void fsp_serialio_config(FSP_S_CONFIG *params, struct soc_intel_skylake_config *config)
+{
+	const unsigned int serialio_devfn[] = {
+		[PchSerialIoIndexI2C0]  = PCH_DEVFN_I2C0,
+		[PchSerialIoIndexI2C1]  = PCH_DEVFN_I2C1,
+		[PchSerialIoIndexI2C2]  = PCH_DEVFN_I2C2,
+		[PchSerialIoIndexI2C3]  = PCH_DEVFN_I2C3,
+		[PchSerialIoIndexI2C4]  = PCH_DEVFN_I2C4,
+		[PchSerialIoIndexI2C5]  = PCH_DEVFN_I2C5,
+		[PchSerialIoIndexSpi0]  = PCH_DEVFN_GSPI0,
+		[PchSerialIoIndexSpi1]  = PCH_DEVFN_GSPI1,
+		[PchSerialIoIndexUart0] = PCH_DEVFN_UART0,
+		[PchSerialIoIndexUart1] = PCH_DEVFN_UART1,
+		[PchSerialIoIndexUart2] = PCH_DEVFN_UART2,
+	};
+	_Static_assert(ARRAY_SIZE(serialio_devfn) == PchSerialIoIndexMax,
+		       "serialio_devfn array size is wrong");
+
+	_Static_assert(!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) ||
+		       (CONFIG_UART_FOR_CONSOLE >= 0 && CONFIG_UART_FOR_CONSOLE <= 2),
+		       "Value for UART_FOR_CONSOLE is invalid");
+
+	for (size_t i = 0; i < ARRAY_SIZE(serialio_devfn); i++) {
+		const bool pcidev_on = is_dev_enabled(pcidev_path_on_root(serialio_devfn[i]));
+		params->SerialIoDevMode[i] = pcidev_on ? PchSerialIoPci : PchSerialIoDisabled;
+	}
+
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) {
+		const size_t i = PchSerialIoIndexUart0 + CONFIG_UART_FOR_CONSOLE;
+		if (params->SerialIoDevMode[i] != PchSerialIoDisabled)
+			params->SerialIoDevMode[i] = PchSerialIoSkipInit;
+	}
+}
+
 /* UPD parameters to be initialized before SiliconInit */
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
@@ -347,8 +382,12 @@

params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);

-	memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
-	       sizeof(params->SerialIoDevMode));
+	if (CONFIG(DERIVE_SERIALIO_CFG_FROM_DEV_STATE)) {
+		fsp_serialio_config(params, config);
+	} else {
+		memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
+		       sizeof(params->SerialIoDevMode));
+	}

dev = pcidev_path_on_root(PCH_DEVFN_CIO);
    params->PchCio2Enable = dev && dev->enabled;