Change in coreboot[master]: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB - coreboot-gerrit

4 Jun 2021


      Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55237 )
Change subject: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB
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Patch Set 1:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/amd_pci_util.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120806):
https://review.coreboot.org/c/coreboot/+/55237/comment/6d34a4a8_a42c84ff 
PS1, Line 56: {
open brace '{' following struct go on the same line
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20
Gerrit-Change-Number: 55237
Gerrit-PatchSet: 1
Gerrit-Owner: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com
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