[L] Change in coreboot[main]: mb/up: Add UP Xtreme mainboard - coreboot-gerrit

2 Feb 2025

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86245?usp=email )
Change subject: mb/up: Add UP Xtreme mainboard
......................................................................
mb/up: Add UP Xtreme mainboard
Change-Id: I0385db8ca798ade5ba90f534134f7fd860fe1aa8
Signed-off-by: Felix Singer felixsinger@posteo.net
---
A src/mainboard/up/xtreme_whl/Kconfig
A src/mainboard/up/xtreme_whl/Kconfig.name
A src/mainboard/up/xtreme_whl/Makefile.mk
A src/mainboard/up/xtreme_whl/board_info.txt
A src/mainboard/up/xtreme_whl/bootblock.c
A src/mainboard/up/xtreme_whl/data.vbt
A src/mainboard/up/xtreme_whl/devicetree.cb
A src/mainboard/up/xtreme_whl/dsdt.asl
A src/mainboard/up/xtreme_whl/gma-mainboard.ads
A src/mainboard/up/xtreme_whl/gpio.c
A src/mainboard/up/xtreme_whl/gpio_early.c
A src/mainboard/up/xtreme_whl/hda_verb.c
A src/mainboard/up/xtreme_whl/include/mainboard/early_stages.h
A src/mainboard/up/xtreme_whl/include/mainboard/ramstage.h
A src/mainboard/up/xtreme_whl/ramstage.c
A src/mainboard/up/xtreme_whl/romstage.c
A src/mainboard/up/xtreme_whl/spd/4g.spd.hex
A src/mainboard/up/xtreme_whl/spd/8g.spd.hex
18 files changed, 268 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/86245/1

diff --git a/src/mainboard/up/xtreme_whl/Kconfig b/src/mainboard/up/xtreme_whl/Kconfig
new file mode 100644
index 0000000..1d1502e
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/Kconfig
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if BOARD_UP_XTREME_WHL
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_32768
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+#	select HAVE_CMOS_DEFAULT	# TODO
+#	select HAVE_OPTION_TABLE	# TODO
+	select HAVE_SPD_IN_CBFS		# TODO
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_WHISKEYLAKE
+	select SUPERIO_FINTEK_F81801
+
+config MAINBOARD_DIR
+	default "up/xtreme_whl"
+
+config MAINBOARD_PART_NUMBER
+	default "Xtreme"
+
+config UART_FOR_CONSOLE
+	default 0
+
+config POST_IO
+	default n
+
+config POST_DEVICE
+	default n
+
+config CONSOLE_POST
+	default y
+
+endif
diff --git a/src/mainboard/up/xtreme_whl/Kconfig.name b/src/mainboard/up/xtreme_whl/Kconfig.name
new file mode 100644
index 0000000..d22fba4
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/Kconfig.name
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+config BOARD_UP_XTREME_WHL
+	bool "Xtreme Whiskey Lake"
diff --git a/src/mainboard/up/xtreme_whl/Makefile.mk b/src/mainboard/up/xtreme_whl/Makefile.mk
new file mode 100644
index 0000000..986befd
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/Makefile.mk
@@ -0,0 +1,16 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += gpio_early.c
+
+romstage-y += romstage.c
+
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+
+SPD_SOURCES += 4g
+SPD_SOURCES += 8g
diff --git a/src/mainboard/up/xtreme_whl/board_info.txt b/src/mainboard/up/xtreme_whl/board_info.txt
new file mode 100644
index 0000000..e361f9f
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/board_info.txt
@@ -0,0 +1,7 @@
+Vendor name: Up
+Board name: Xtreme
+Category: mini
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2019
diff --git a/src/mainboard/up/xtreme_whl/bootblock.c b/src/mainboard/up/xtreme_whl/bootblock.c
new file mode 100644
index 0000000..8cab844
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootblock_common.h>
+#include <mainboard/early_stages.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	configure_early_gpios();
+}
diff --git a/src/mainboard/up/xtreme_whl/data.vbt b/src/mainboard/up/xtreme_whl/data.vbt
new file mode 100644
index 0000000..c1b3548
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/data.vbt
Binary files differ
diff --git a/src/mainboard/up/xtreme_whl/devicetree.cb b/src/mainboard/up/xtreme_whl/devicetree.cb
new file mode 100644
index 0000000..cb89335
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/devicetree.cb
@@ -0,0 +1,29 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/cannonlake
+	device domain 0 on
+		device ref igpu on end
+		device ref dptf on end
+		device ref thermal on end
+		device ref xhci on end
+		device ref sata on
+			register "SataSalpSupport" = "1"
+			register "SataPortsEnable[0]" = "1"
+		end
+		device ref emmc on	end
+		device ref pcie_rp5 on	end
+		device ref pcie_rp6 on	end
+		device ref pcie_rp7 on	end
+		device ref pcie_rp8 on	end
+		device ref pcie_rp9 on	end
+		device ref pcie_rp10 on	end
+		device ref pcie_rp14 on	end
+		device ref pcie_rp15 on	end
+		device ref pcie_rp16 on	end
+		device ref uart0 on	end
+		device ref hda on	end
+		device ref smbus on	end
+		device ref fast_spi on	end
+		device ref gbe on	end
+	end
+end
diff --git a/src/mainboard/up/xtreme_whl/dsdt.asl b/src/mainboard/up/xtreme_whl/dsdt.asl
new file mode 100644
index 0000000..392a79a
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	Device (_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/up/xtreme_whl/gma-mainboard.ads b/src/mainboard/up/xtreme_whl/gma-mainboard.ads
new file mode 100644
index 0000000..e0a166f
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/gma-mainboard.ads
@@ -0,0 +1,15 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (eDP,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/up/xtreme_whl/gpio.c b/src/mainboard/up/xtreme_whl/gpio.c
new file mode 100644
index 0000000..ac06144
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/gpio.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/gpio.h>
+#include <mainboard/ramstage.h>
+
+static const struct pad_config gpio_table[] = { 0 };
+
+void configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/up/xtreme_whl/gpio_early.c b/src/mainboard/up/xtreme_whl/gpio_early.c
new file mode 100644
index 0000000..26d87d4
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/gpio_early.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/gpio.h>
+#include <mainboard/early_stages.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPI(GPP_A18, NONE, DEEP),	/* DDR_ID1 */
+	PAD_CFG_GPI(GPP_A23, NONE, DEEP),	/* DDR_ID2 */
+	PAD_CFG_GPI(GPP_C8, NONE, DEEP),	/* BRD_ID0 */
+	PAD_CFG_GPI(GPP_C9, NONE, DEEP),	/* BRD_ID1 */
+	PAD_CFG_GPI(GPP_C10, NONE, DEEP),	/* BRD_ID2 */
+	PAD_CFG_GPI(GPP_C11, NONE, DEEP),	/* DDR_ID0 */
+};
+
+void configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/up/xtreme_whl/hda_verb.c b/src/mainboard/up/xtreme_whl/hda_verb.c
new file mode 100644
index 0000000..d3619ab
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/hda_verb.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = { };
+
+const u32 pc_beep_verbs[] = { };
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/up/xtreme_whl/include/mainboard/early_stages.h b/src/mainboard/up/xtreme_whl/include/mainboard/early_stages.h
new file mode 100644
index 0000000..bc476af
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/include/mainboard/early_stages.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+void configure_early_gpios(void);
diff --git a/src/mainboard/up/xtreme_whl/include/mainboard/ramstage.h b/src/mainboard/up/xtreme_whl/include/mainboard/ramstage.h
new file mode 100644
index 0000000..2029d0f
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/include/mainboard/ramstage.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+void configure_gpios(void);
diff --git a/src/mainboard/up/xtreme_whl/ramstage.c b/src/mainboard/up/xtreme_whl/ramstage.c
new file mode 100644
index 0000000..f0daa93
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/ramstage.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/device.h>
+#include <mainboard/ramstage.h>
+
+static void init_mainboard(void *chip_info)
+{
+	configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = init_mainboard,
+};
diff --git a/src/mainboard/up/xtreme_whl/romstage.c b/src/mainboard/up/xtreme_whl/romstage.c
new file mode 100644
index 0000000..73fa78e
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/romstage.c
@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
diff --git a/src/mainboard/up/xtreme_whl/spd/4g.spd.hex b/src/mainboard/up/xtreme_whl/spd/4g.spd.hex
new file mode 100644
index 0000000..8642bc1
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/spd/4g.spd.hex
@@ -0,0 +1,32 @@
+23 11 0c 03 45 21 00 08 00 60 00 03 02 03 80 00
+00 00 07 0d f8 0f 00 00 6e 6e 6e 11 00 6e f0 0a
+20 08 00 05 00 f0 2b 34 28 00 78 00 14 3c 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0b 35
+16 36 0b 35 00 00 16 36 0b 35 16 36 0b 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9c b5 00 00 00 00 e7 d6 b8 4a
+0f 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0 e2
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+08 f7 4b 00 00 00 00 00 00 44 34 53 53 31 32 31
+36 31 53 48 32 34 41 2d 42 20 20 20 20 00 80 ce
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/up/xtreme_whl/spd/8g.spd.hex b/src/mainboard/up/xtreme_whl/spd/8g.spd.hex
new file mode 100644
index 0000000..b28d68b
--- /dev/null
+++ b/src/mainboard/up/xtreme_whl/spd/8g.spd.hex
@@ -0,0 +1,32 @@
+23 11 0c 03 85 21 00 08 00 60 00 03 01 03 00 00
+00 00 07 0d f8 0f 00 00 6e 6e 6e 11 00 6e f0 0a
+20 08 00 05 00 a8 1b 28 28 00 78 00 14 3c 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0b 35
+16 36 0b 35 00 00 16 36 0b 35 16 36 0b 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9c b5 00 00 00 00 e7 d6 89 02
+0f 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0 e2
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 ad 01 00 00 00 00 00 00 48 4d 41 41 35 31 53
+36 41 4d 52 36 4e 2d 55 48 20 20 20 20 00 80 ad
+ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 dd 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/86245?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email

Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I0385db8ca798ade5ba90f534134f7fd860fe1aa8
Gerrit-Change-Number: 86245
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer service+coreboot-gerrit@felixsinger.de



    