Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37620 )
Change subject: soc/intel/cannonlake: Make Heci configurable ......................................................................
soc/intel/cannonlake: Make Heci configurable
This patch adds functionality to disable/enable Heci via devicetree like register "HeciCommunication2" = "1".
Change-Id: Ifa5b1440b4d6622cef0bfe82dc22a81b55f12bda Signed-off-by: Christian Walter christian.walter@9elements.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/fsp_params.c 3 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/37620/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f08fd0a..9180fb7 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -231,6 +231,8 @@ /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; + uint8_t Heci1Disabled; + uint8_t HeciCommunication2;
/* PL1 Override value in Watts */ uint32_t tdp_pl1_override; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dfc7e22..ac85d2b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -370,6 +370,9 @@ params->Heci3Enabled = config->Heci3Enabled; #if !CONFIG(HECI_DISABLE_USING_SMM) params->Heci1Disabled = !config->HeciEnabled; +#else + if (config->Heci1Disabled) + params->Heci1Disabled = config->Heci1Disabled; #endif params->Device4Enable = config->Device4Enable;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5c74d4a..faa7dff 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -124,6 +124,9 @@ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT;
+ if (config->HeciCommunication2) + tconfig->HeciCommunication2 = config->HeciCommunication2; + /* Configure VT-d */ tconfig->VtdDisable = 0;
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37620
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Make Heci configurable ......................................................................
soc/intel/cannonlake: Make Heci configurable
This patch adds functionality to disable/enable Heci1 Device via params, e.g.: set register "Heci1Disabled" = "1" in the devicetree.
Change-Id: Ifa5b1440b4d6622cef0bfe82dc22a81b55f12bda Signed-off-by: Christian Walter christian.walter@9elements.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/37620/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37620 )
Change subject: soc/intel/cannonlake: Make Heci configurable ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37620/2/src/soc/intel/cannonlake/fs... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/37620/2/src/soc/intel/cannonlake/fs... PS2, Line 371: #if !CONFIG(HECI_DISABLE_USING_SMM) : params->Heci1Disabled = !config->HeciEnabled; : #endif Convert that to C if?
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37620 )
Change subject: soc/intel/cannonlake: Make Heci configurable ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37620/6/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37620/6/src/soc/intel/cannonlake/ch... PS6, Line 233: uint8_t HeciEnabled; it's already here, why do you need to add it again?
Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37620 )
Change subject: soc/intel/cannonlake: Make Heci configurable ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37620/6/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37620/6/src/soc/intel/cannonlake/ch... PS6, Line 233: uint8_t HeciEnabled;
it's already here, why do you need to add it again?
I cant find it... where is it already?
Christian Walter has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37620 )
Change subject: soc/intel/cannonlake: Make Heci configurable ......................................................................
Abandoned
Not needed anymore.
-
Christian Walter (Code Review) -
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)