Change in coreboot[master]: Revert "soc/intel/jasperlake: Allow mainboard to override chip config...

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46653 )

Change subject: Revert "soc/intel/jasperlake: Allow mainboard to override chip configuration"
......................................................................

Revert "soc/intel/jasperlake: Allow mainboard to override chip configuration"

This reverts commit 5acea15d63e821a1bc416d206162ed030cd5d57c. This
change got accidentally merged. There is no need for mainboard to
override chip configuration.

BUG=None
TEST=Build and boot Drawlat to OS.

Change-Id: I166ba7e5ee50a6329032eae8e17b9a554b094e2e
Signed-off-by: Karthikeyan Ramasubramanian 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46653
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Angel Pons 
---
M src/soc/intel/jasperlake/fsp_params.c
M src/soc/intel/jasperlake/include/soc/ramstage.h
2 files changed, 0 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index cb0070a8..db27234 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -78,11 +78,6 @@
    	sizeof(config->SerialIoUartMode));
 }

-__weak void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config)
-{
-	/* Override settings per board. */
-}
-
 /* UPD parameters to be initialized before SiliconInit */
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
@@ -91,9 +86,6 @@
    FSP_S_CONFIG *params = &supd->FspsConfig;
    struct soc_intel_jasperlake_config *config = config_of_soc();

-	/* Allow mainboard to override any chip config */
-	mainboard_update_soc_chip_config(config);
-
    /* Parse device tree and fill in FSP UPDs */
    parse_devicetree(params);

diff --git a/src/soc/intel/jasperlake/include/soc/ramstage.h b/src/soc/intel/jasperlake/include/soc/ramstage.h
index 1de8e37..8188fbd 100644
--- a/src/soc/intel/jasperlake/include/soc/ramstage.h
+++ b/src/soc/intel/jasperlake/include/soc/ramstage.h
@@ -9,7 +9,6 @@
 #include <soc/soc_chip.h>

void mainboard_silicon_init_params(FSP_S_CONFIG *params);
-void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *config);
 void soc_init_pre_device(void *chip_info);

#endif