Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19512 )
Change subject: WIP LAPIC udelay ......................................................................
WIP LAPIC udelay
Change-Id: I98374a176e1a08a199fc47c9f4b77ee70a23c9dd Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/i945/Makefile.inc M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/raminit.h D src/northbridge/intel/i945/udelay.c 4 files changed, 1 insertion(+), 80 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/19512/1
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 0e4fcfc..9dba2ac 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -27,6 +27,4 @@ romstage-y += debug.c romstage-y += rcven.c
-smm-y += udelay.c - endif diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 7f44f15..fb78de7 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -19,6 +19,7 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <device/device.h> +#include <delay.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 2db7d3b..60787f5 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -70,7 +70,6 @@ void receive_enable_adjust(struct sys_info *sysinfo); void sdram_initialize(int boot_path, const u8 *sdram_addresses); int fixup_i945_errata(void); -void udelay(u32 us);
#if CONFIG_DEBUG_RAM_SETUP void sdram_dump_mchbar_registers(void); diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c deleted file mode 100644 index 90f2638..0000000 --- a/src/northbridge/intel/i945/udelay.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> -#include <cpu/intel/speedstep.h> - -/** - * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock - */ - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 fsb = 0, divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(MSR_FSB_FREQ); - switch (msr.lo & 0x07) { - case 5: - fsb = 400; - break; - case 1: - fsb = 533; - break; - case 3: - fsb = 667; - break; - case 2: - fsb = 800; - break; - case 0: - fsb = 1067; - break; - case 4: - fsb = 1333; - break; - case 6: - fsb = 1600; - break; - } - - msr = rdmsr(0x198); - divisor = (msr.hi >> 8) & 0x1f; - - d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ - - multiply_to_tsc(&tscd, us, d); - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) - tsc1.hi++; - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); -}
-
Arthur Heymans (Code Review)