[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2
Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72737 )
Change subject: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 ......................................................................
soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2
Now that the PCIe ports on device 1 are added, rename the aliases for the PCIe ports on device 2 to have a common naming scheme.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/soc/amd/phoenix/chipset.cb 3 files changed, 26 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/72737/1
diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index a4f18a3..59d4043 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -158,9 +158,9 @@
device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_0 on end # GBE + device ref gpp_bridge_2_1 on end # WIFI + device ref gpp_bridge_2_2 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index ec88892..01801ff 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -158,9 +158,9 @@
device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_0 on end # GBE + device ref gpp_bridge_2_1 on end # WIFI + device ref gpp_bridge_2_2 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index e314c39..cd3affa 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -15,12 +15,13 @@ device pci 01.3 alias gpp_bridge_1_2 off ops amd_external_pcie_gpp_ops end
device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_2_0 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end + device pci 02.7 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end
device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A
-
Felix Held (Code Review)