[S] Change in coreboot[master]: mb/google/brya: Enable asynchronous End-Of-Post

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli, Jérémy Compostella.

Hello Jérémy Compostella,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/74215

to review the following change.

Change subject: mb/google/brya: Enable asynchronous End-Of-Post
......................................................................

mb/google/brya: Enable asynchronous End-Of-Post

Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.

With these settings we have observed a boot time reduction of about 20
to 30 ms on brya0.

BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
     End-Of-Post after PCI initialization and EOP message received at
     `BS_PAYLOAD_BOOT'.

Signed-off-by: Jeremy Compostella 
Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41
---
M src/mainboard/google/brya/Kconfig
M src/soc/intel/alderlake/Kconfig
2 files changed, 25 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/74215/1

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 9ae944d..e588524 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -32,6 +32,7 @@
    select PMC_IPC_ACPI_INTERFACE
    select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
    select SOC_INTEL_CSE_LITE_SKU
+	select SOC_INTEL_CSE_SEND_EOP_ASYNC
    select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P
    select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE
    select SOC_INTEL_CRASHLOG
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 1bc84ce..2887439 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -122,7 +122,7 @@
    select SOC_INTEL_COMMON_FSP_RESET
    select SOC_INTEL_COMMON_PCH_CLIENT
    select SOC_INTEL_COMMON_RESET
-	select SOC_INTEL_CSE_SEND_EOP_LATE
+	select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON
    select SOC_INTEL_CSE_SET_EOP
    select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
    select HAVE_INTEL_COMPLIANCE_TEST_MODE