Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56227 )
Change subject: soc/amd/cezanne: Move APOB update into ramstage ......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56227/comment/db23610a_8c0afd3b PS2, Line 10: it into ramstage allow us to use threads to pre-load the apob from SPI.
Does it offer boot time savings? If so, can you please capture in the commit message regarding how m […]
I thought we were storing the APOB to SPI in coreboot, where PSP is loading the APOB from SPI. Did I miss something? Are you really intending to optimize the compare instead? And could we simplify that whole piece by just hashing it instead?
/* Save APOB buffer to flash */ void soc_update_apob_cache(void)
https://review.coreboot.org/c/coreboot/+/56227/comment/6a5d35c9_ca066a9a PS2, Line 13: and picasso
Nit: Zork and Guybrush?
Nit the Nit: Trembyle (or equiv) and Guybrush.
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Eric Peers (Code Review)