Change in coreboot[master]: [WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs - coreboot-gerrit

4 Nov 2021

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58968 )
Change subject: [WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs
......................................................................
[WIP] drivers/mrc_cache: Drop get_write_protect_state() stubs
It should be optional to protect MRC_CACHE without
CHROMEOS so MRC_SETTINGS_PROTECT cannot be enforced
from soc/.
This change selects MRC_SETTINGS_PROTECT also for older
platforms when CHROMEOS is selected.
If a board does not implement get_write_protect_state()
MRC_SETTINGS_PROTECT should not be selected since the
related SPI flash pages will not get protected.
Currently, such real implementations may or may not be
guarded with CONFIG(CHROMEOS) and the protection is
only expected to work after followup works.
Change-Id: I8db0394645df1917b686339fa79432ccfc6960a2
Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com
---
M src/drivers/mrc_cache/mrc_cache.c
M src/ec/lenovo/h8/vboot.c
M src/mainboard/amd/majolica/chromeos.c
M src/mainboard/google/foster/chromeos.c
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/coffeelake_rvp/chromeos.c
M src/mainboard/intel/galileo/vboot.c
M src/mainboard/intel/glkrvp/chromeos.c
M src/mainboard/intel/icelake_rvp/chromeos.c
M src/mainboard/intel/jasperlake_rvp/chromeos.c
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/tglrvp/chromeos.c
M src/mainboard/intel/wtm2/chromeos.c
M src/security/vboot/bootmode.c
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/icelake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/skylake/Kconfig
M src/soc/intel/tigerlake/Kconfig
M src/vendorcode/google/chromeos/Kconfig
24 files changed, 4 insertions(+), 86 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/58968/1

diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c
index 841c97e..35d5a0c 100644
--- a/src/drivers/mrc_cache/mrc_cache.c
+++ b/src/drivers/mrc_cache/mrc_cache.c
@@ -506,6 +506,8 @@
    }
 }
+__weak int get_write_protect_state(void) { return 0; }
+
 /* Read flash status register to determine if write protect is active */
 static int nvm_is_write_protected(void)
 {
@@ -513,9 +515,6 @@
    u8 wp_gpio;
    u8 wp_spi;
-	if (!CONFIG(CHROMEOS))
-		return 0;
-
    if (!CONFIG(BOOT_DEVICE_SPI_FLASH))
    	return 0;
diff --git a/src/ec/lenovo/h8/vboot.c b/src/ec/lenovo/h8/vboot.c
index b564153..b38151f 100644
--- a/src/ec/lenovo/h8/vboot.c
+++ b/src/ec/lenovo/h8/vboot.c
@@ -31,12 +31,3 @@
return h8_get_fn_key();
 }
-
-/**
- * Only used if CONFIG(CHROMEOS) is set.
- * Always zero as the #WP pin of the flash is tied high.
- */
-int get_write_protect_state(void)
-{
-	return 0;
-}
diff --git a/src/mainboard/amd/majolica/chromeos.c b/src/mainboard/amd/majolica/chromeos.c
index 5fecbe0..3311809 100644
--- a/src/mainboard/amd/majolica/chromeos.c
+++ b/src/mainboard/amd/majolica/chromeos.c
@@ -1,14 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <bootmode.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-int get_write_protect_state(void)
-{
-	/* Majolica doesn't have a write protect pin */
-	return 0;
-}
-
 const struct cros_gpio *variant_cros_gpios(size_t *num)
 {
    /* No ChromeOS GPIOs */
diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c
index 4e744f1..79a83f8 100644
--- a/src/mainboard/google/foster/chromeos.c
+++ b/src/mainboard/google/foster/chromeos.c
@@ -22,7 +22,3 @@
    return 0;
 }
-int get_write_protect_state(void)
-{
-	return 0;
-}
diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c
index dc2f1b3..4c021cd 100644
--- a/src/mainboard/intel/adlrvp/chromeos.c
+++ b/src/mainboard/intel/adlrvp/chromeos.c
@@ -32,8 +32,3 @@
 }
 #endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
-int get_write_protect_state(void)
-{
-	/* No write protect */
-	return 0;
-}
diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c
index cf90889..1b18664 100644
--- a/src/mainboard/intel/coffeelake_rvp/chromeos.c
+++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c
@@ -27,8 +27,3 @@
    return 0;
 }
-int get_write_protect_state(void)
-{
-	/* No write protect */
-	return 0;
-}
diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c
index 4a7f424..8f627c5 100644
--- a/src/mainboard/intel/galileo/vboot.c
+++ b/src/mainboard/intel/galileo/vboot.c
@@ -17,12 +17,6 @@
    return 0;
 }
-int get_write_protect_state(void)
-{
-	/* Not write protected */
-	return 0;
-}
-
 void verstage_mainboard_init(void)
 {
    const struct reg_script *script;
diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c
index c48a2ce..11e0c7e 100644
--- a/src/mainboard/intel/glkrvp/chromeos.c
+++ b/src/mainboard/intel/glkrvp/chromeos.c
@@ -18,11 +18,6 @@
    lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
-int get_write_protect_state(void)
-{
-	return 0;
-}
-
 int __weak get_lid_switch(void)
 {
    return -1;
diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c
index b702d23..d76fba4 100644
--- a/src/mainboard/intel/icelake_rvp/chromeos.c
+++ b/src/mainboard/intel/icelake_rvp/chromeos.c
@@ -27,8 +27,3 @@
    return 0;
 }
-int get_write_protect_state(void)
-{
-	/* No write protect */
-	return 0;
-}
diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c
index b66b4bf..0b9dda6 100644
--- a/src/mainboard/intel/jasperlake_rvp/chromeos.c
+++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c
@@ -29,8 +29,3 @@
#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
-int get_write_protect_state(void)
-{
-	/* No write protect */
-	return 0;
-}
diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c
index e026917..6f6c938 100644
--- a/src/mainboard/intel/kblrvp/chromeos.c
+++ b/src/mainboard/intel/kblrvp/chromeos.c
@@ -48,12 +48,6 @@
    return 0;
 }
-int get_write_protect_state(void)
-{
-	/* No write protect */
-	return 0;
-}
-
 static const struct cros_gpio cros_gpios[] = {
    CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
    CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c
index 328429d..39b3597 100644
--- a/src/mainboard/intel/tglrvp/chromeos.c
+++ b/src/mainboard/intel/tglrvp/chromeos.c
@@ -30,8 +30,3 @@
#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
-int get_write_protect_state(void)
-{
-	/* No write protect */
-	return 0;
-}
diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c
index 57d51e79..42566aa 100644
--- a/src/mainboard/intel/wtm2/chromeos.c
+++ b/src/mainboard/intel/wtm2/chromeos.c
@@ -25,11 +25,6 @@
    return REC_MODE_SETTING;
 }
-int get_write_protect_state(void)
-{
-	return 0;
-}
-
 static const struct cros_gpio cros_gpios[] = {
    CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
    CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c
index c4c6441..ccd0584 100644
--- a/src/security/vboot/bootmode.c
+++ b/src/security/vboot/bootmode.c
@@ -59,14 +59,8 @@
#if CONFIG(VBOOT_NO_BOARD_SUPPORT)
 /**
- * TODO: Create flash protection interface which implements get_write_protect_state.
- * get_recovery_mode_switch should be implemented as default function.
+ * TODO: get_recovery_mode_switch should be implemented as default function.
  */
-int __weak get_write_protect_state(void)
-{
-	return 0;
-}
-
 int __weak get_recovery_mode_switch(void)
 {
    return 0;
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index f646fc7..24df9b8 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -36,7 +36,6 @@
    select INTEL_GMA_OPREGION_2_1
    select INTEL_TME
    select MP_SERVICES_PPI_V2
-	select MRC_SETTINGS_PROTECT
    select PARALLEL_MP_AP_WORK
    select MICROCODE_BLOB_UNDISCLOSED
    select PLATFORM_USES_FSP2_2
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 45e21dd..d6eff1d 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -44,7 +44,6 @@
    select INTEL_DESCRIPTOR_MODE_CAPABLE
    select HAVE_SMI_HANDLER
    select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE
-	select MRC_SETTINGS_PROTECT
    select MRC_SETTINGS_VARIABLE_DATA
    select NO_XIP_EARLY_STAGES
    select NO_PM_ACPI_TIMER
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index f02e810..e9dc961 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -10,7 +10,6 @@
    select CACHE_MRC_SETTINGS
    select CPU_INTEL_HASWELL
    select INTEL_GMA_ACPI
-	select MRC_SETTINGS_PROTECT
    select REG_SCRIPT
config BROADWELL_VBOOT_IN_BOOTBLOCK
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 29315a1..0f621c0 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -67,7 +67,6 @@
    select INTEL_DESCRIPTOR_MODE_CAPABLE
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
-	select MRC_SETTINGS_PROTECT
    select PARALLEL_MP_AP_WORK
    select PLATFORM_USES_FSP2_0
    select PM_ACPI_TIMER_OPTIONAL
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index f23e8d7..501d09d 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -26,7 +26,6 @@
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
    select MP_SERVICES_PPI_V1
-	select MRC_SETTINGS_PROTECT
    select PARALLEL_MP_AP_WORK
    select MICROCODE_BLOB_UNDISCLOSED
    select PLATFORM_USES_FSP2_1
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 0f0665b..2ff5e3b 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -26,7 +26,6 @@
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
    select MP_SERVICES_PPI_V1
-	select MRC_SETTINGS_PROTECT
    select PARALLEL_MP_AP_WORK
    select MICROCODE_BLOB_UNDISCLOSED
    select PLATFORM_USES_FSP2_1
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index afa7a23..35df757 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -27,7 +27,6 @@
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
    select MP_SERVICES_PPI_V1
-	select MRC_SETTINGS_PROTECT
    select PARALLEL_MP_AP_WORK
    select MICROCODE_BLOB_UNDISCLOSED
    select PLATFORM_USES_FSP2_2
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 6c8a376..250eef7 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -41,7 +41,6 @@
    select INTEL_DESCRIPTOR_MODE_CAPABLE
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
-	select MRC_SETTINGS_PROTECT
    select PARALLEL_MP_AP_WORK
    select PLATFORM_USES_FSP2_0
    select PM_ACPI_TIMER_OPTIONAL
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 7a78f22..33cae78 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -36,7 +36,6 @@
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
    select MP_SERVICES_PPI_V1
-	select MRC_SETTINGS_PROTECT
    select PARALLEL_MP_AP_WORK
    select PLATFORM_USES_FSP2_2
    select PM_ACPI_TIMER_OPTIONAL
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 36ca023..6f4d198 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -15,6 +15,7 @@
    select CHROMEOS_NVS if ACPI_SOC_NVS
    select VPD
    select VBOOT_SLOTS_RW_AB
+	select MRC_SETTINGS_PROTECT if CACHE_MRC_SETTINGS
    help
      Enable ChromeOS specific features like the GPIO sub table in
      the coreboot table. NOTE: Enabling this option on an unsupported
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/58968
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8db0394645df1917b686339fa79432ccfc6960a2
Gerrit-Change-Number: 58968
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki kyosti.malkki@gmail.com
Gerrit-MessageType: newchange



    