Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi
BUG=none BRANCH=none TEST=Build and boot volteer
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39333/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b9ed424..6ef54d4 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -226,7 +226,11 @@ device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 off end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + device pci 14.3 on + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + end + end # CNVi: WiFi 0xA0F0 - A0F3
device pci 15.0 on chip drivers/i2c/generic
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 1: Code-Review+1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 1: Code-Review+2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 1:
Don't we need to define DRIVERS_INTEL_WIFI or DRIVERS_GENERIC_WIFI in Kconfig in mainboard Kconfig?
~/data/corebootorg/coreboot/src/drivers/intel/wifi$ cat Kconfig
config DRIVERS_INTEL_WIFI bool "Support Intel PCI-e WiFi adapters" depends on PCI default y if PCIEXP_PLUGIN_SUPPORT select DRIVERS_GENERIC_WIFI if HAVE_ACPI_TABLES help When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39333/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39333/1//COMMIT_MSG@10 PS1, Line 10: adds dynamic SSDT entires for CNVi also export wake gpio for CNVi Please add at dot/period at the end of a sentence.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 1:
Patch Set 1:
Don't we need to define DRIVERS_INTEL_WIFI or DRIVERS_GENERIC_WIFI in Kconfig in mainboard Kconfig?
~/data/corebootorg/coreboot/src/drivers/intel/wifi$ cat Kconfig
config DRIVERS_INTEL_WIFI bool "Support Intel PCI-e WiFi adapters" depends on PCI default y if PCIEXP_PLUGIN_SUPPORT select DRIVERS_GENERIC_WIFI if HAVE_ACPI_TABLES help When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets.
DRIVERS_INTEL_WIFI is selected
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39333
to look at the new patch set (#2).
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi.
BUG=none BRANCH=none TEST=Build and boot volteer
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39333/2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39333/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39333/1//COMMIT_MSG@10 PS1, Line 10: adds dynamic SSDT entires for CNVi also export wake gpio for CNVi
Please add at dot/period at the end of a sentence.
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 2: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/39333/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39333/2/src/mainboard/google/voltee... PS2, Line 229: device pci 14.3 on : chip drivers/intel/wifi : register "wake" = "GPE0_PME_B0" : end : end # CNVi: WiFi This is not correct. There is no device that you are adding under chip drivers/intel/wifi.
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39333
to look at the new patch set (#3).
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi.
BUG=none BRANCH=none TEST=Build and boot volteer
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39333/3
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39333/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39333/2/src/mainboard/google/voltee... PS2, Line 229: device pci 14.3 on : chip drivers/intel/wifi : register "wake" = "GPE0_PME_B0" : end : end # CNVi: WiFi
This is not correct. There is no device that you are adding under chip drivers/intel/wifi.
Fixed.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 3: Code-Review+2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi.
BUG=none BRANCH=none TEST=Build and boot volteer
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39333 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 4 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Nick Vaccaro: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b9ed424..70b6186 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -226,7 +226,10 @@ device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 off end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + end
device pci 15.0 on chip drivers/i2c/generic
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39333 )
Change subject: mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1197 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1196 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1195
Please note: This test is under development and might not be accurate at all!