Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30609
Change subject: [WIP]cbmem_top: Fix comment and remove upper limit ......................................................................
[WIP]cbmem_top: Fix comment and remove upper limit
There's no such limit on 64bit coreboot builds. * Fix comment * Remove 4 GiB limit on Cavium SoCs
Change-Id: I8c9c6a5ff81bee48311e8bf8e383d1a032ea3a6d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/include/cbmem.h M src/soc/cavium/cn81xx/cbmem.c 2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/30609/1
diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ad48e35..66a8fbe 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -71,7 +71,8 @@
/* Return the top address for dynamic cbmem. The address returned needs to * be consistent across romstage and ramstage, and it is required to be - * below 4GiB. + * below 4GiB for 32bit coreboot builds. On 64bit coreboot builds there's no + * upper limit. * x86 boards or chipsets must return NULL before the cbmem backing store has * been initialized. */ void *cbmem_top(void); diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index 397fd26..9a52de3 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -22,6 +22,5 @@ void *cbmem_top(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB, - 4ULL * GiB); + return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); }
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30609
to look at the new patch set (#2).
Change subject: cbmem_top: Fix comment and remove upper limit ......................................................................
cbmem_top: Fix comment and remove upper limit
There's no such limit on 64 Bit coreboot builds.
* Fix comment in cbmem.h * Remove 4 GiB limit on Cavium SoCs
Tested on opencellular/elgon. Still boots Linux as payload.
Change-Id: I8c9c6a5ff81bee48311e8bf8e383d1a032ea3a6d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/include/cbmem.h M src/soc/cavium/cn81xx/cbmem.c 2 files changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/30609/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30609 )
Change subject: cbmem_top: Fix comment and remove upper limit ......................................................................
Patch Set 2: Code-Review+1
Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30609 )
Change subject: cbmem_top: Fix comment and remove upper limit ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30609 )
Change subject: cbmem_top: Fix comment and remove upper limit ......................................................................
cbmem_top: Fix comment and remove upper limit
There's no such limit on 64 Bit coreboot builds.
* Fix comment in cbmem.h * Remove 4 GiB limit on Cavium SoCs
Tested on opencellular/elgon. Still boots Linux as payload.
Change-Id: I8c9c6a5ff81bee48311e8bf8e383d1a032ea3a6d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/30609 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Stefan Reinauer stefan.reinauer@coreboot.org --- M src/include/cbmem.h M src/soc/cavium/cn81xx/cbmem.c 2 files changed, 4 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve
diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 59f4e10..680284a 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -70,7 +70,8 @@
/* Return the top address for dynamic cbmem. The address returned needs to * be consistent across romstage and ramstage, and it is required to be - * below 4GiB. + * below 4GiB for 32bit coreboot builds. On 64bit coreboot builds there's no + * upper limit. * x86 boards or chipsets must return NULL before the cbmem backing store has * been initialized. */ void *cbmem_top(void); diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index 397fd26..bb6fa18 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2014 Rockchip Inc. + * Copyright 2019 9Elements GmbH patrick.rudolph@9elements.com * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +23,5 @@ void *cbmem_top(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB, - 4ULL * GiB); + return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); }
-
Patrick Georgi (Code Review) -
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)
-
Stefan Reinauer (Code Review)