Change in coreboot[master]: soc/intel/skylake: lockdown: lock global reset

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36573 )

Change subject: soc/intel/skylake: lockdown: lock global reset
......................................................................

soc/intel/skylake: lockdown: lock global reset

There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only
one (apollolake) is actually calling the code. Add the missing call.

Also fix the register offset in a comment in reset code.

Tested successfully on X11SSM-F by reading ETR3.

Change-Id: If190c3c66889ede105d958b423b38ebdcb698332
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36573
Reviewed-by: Aaron Durbin 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/skylake/lockdown.c
M src/soc/intel/skylake/reset.c
2 files changed, 5 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved

diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index 69459e7..66dae8c 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -16,6 +16,7 @@
 #include <device/mmio.h>
 #include <intelblocks/cfg.h>
 #include <intelblocks/lpc_lib.h>
+#include <intelblocks/pmclib.h>
 #include <intelpch/lockdown.h>
 #include <soc/pm.h>

@@ -38,6 +39,9 @@
    pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
    pmsyncreg |= PMSYNC_LOCK;
    write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
+
+	/* Make sure payload/OS can't trigger global reset */
+	pmc_global_reset_disable_and_lock();
 }

void soc_lockdown_config(int chipset_lockdown)
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index ff1a959..8f5bf30 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -26,7 +26,7 @@
    /*
     * BIOS should ensure it does a global reset
     * to reset both host and Intel ME by setting
-	 * PCH PMC [B0:D31:F2 register offset 0x1048 bit 20]
+	 * PCH PMC [B0:D31:F2 register offset 0xAC bit 20]
     */
    pmc_global_reset_enable(true);