[XS] Change in coreboot[main]: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS

[Shuo Liu (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80795?usp=email )

Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS
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Patch Set 2:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/80795/comment/4a8ff6a6_f379fa27 :
PS1, Line 10: hidden the fast_spi driver will generate the _CRS marking the BAR
> Updated the commit message to clarify.

If the device is hidden, configuration space read will return invalid values, hence we cannot get the BAR address through the configuration read. Could you please help to point me the code in fast-spi driver that can handle this?