EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35113 )
Change subject: mb/google/drallion: add dummy SPD file ......................................................................
mb/google/drallion: add dummy SPD file
Drallion will use solder down memory. Add dummy spd file.
BUG=b:139397313 BRANCH=N/A TEST=Build and check cbfs has the dummy spd.bin
Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220 Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/spd/Makefile.inc A src/mainboard/google/drallion/spd/empty_ddr4.spd.hex M src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc 7 files changed, 77 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/35113/1
diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index cff56a4..2484ce7 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -8,7 +8,6 @@ select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_GOOGLE_WILCO - select GENERIC_SPD_BIN select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -19,7 +18,6 @@ select SOC_INTEL_COMETLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE - select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP select TPM2 select MAINBOARD_USES_IFD_EC_REGION diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc index c16e7d2..e7c90bb 100644 --- a/src/mainboard/google/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/Makefile.inc @@ -36,3 +36,5 @@
subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += spd diff --git a/src/mainboard/google/drallion/spd/Makefile.inc b/src/mainboard/google/drallion/spd/Makefile.inc new file mode 100644 index 0000000..e35544b --- /dev/null +++ b/src/mainboard/google/drallion/spd/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +ifeq ($(SPD_SOURCES),) + SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) +else + SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +endif + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/drallion/spd/empty_ddr4.spd.hex b/src/mainboard/google/drallion/spd/empty_ddr4.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/google/drallion/spd/empty_ddr4.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc b/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc index 2bf028e..1cc010c 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc +++ b/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc @@ -13,6 +13,9 @@ ## GNU General Public License for more details. ##
+## GPP_F12-F16 indicates mem_id to match specific spd file +SPD_SOURCES = empty_ddr4 # 0b00000 + bootblock-y += gpio.c ramstage-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 2bf028e..0400d33 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -13,6 +13,9 @@ ## GNU General Public License for more details. ##
+## GPP_F12-F16 indicates mem_id to match specific spd file +SPD_SOURCES = empty_ddr4 # 0b00000 + bootblock-y += gpio.c ramstage-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc b/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc index 2bf028e..1cc010c 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc +++ b/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc @@ -13,6 +13,9 @@ ## GNU General Public License for more details. ##
+## GPP_F12-F16 indicates mem_id to match specific spd file +SPD_SOURCES = empty_ddr4 # 0b00000 + bootblock-y += gpio.c ramstage-y += gpio.c romstage-y += gpio.c
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35113 )
Change subject: mb/google/drallion: add dummy SPD file ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35113/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35113/1//COMMIT_MSG@9 PS1, Line 9: solder soldered
Hello Selma Bensaid, Mathew King, Lijian Zhao, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35113
to look at the new patch set (#2).
Change subject: mb/google/drallion: add dummy SPD file ......................................................................
mb/google/drallion: add dummy SPD file
Drallion will use soldered down memory. Add dummy spd file.
BUG=b:139397313 BRANCH=N/A TEST=Build and check cbfs has the dummy spd.bin
Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220 Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/spd/Makefile.inc A src/mainboard/google/drallion/spd/empty_ddr4.spd.hex M src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc 7 files changed, 77 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/35113/2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35113 )
Change subject: mb/google/drallion: add dummy SPD file ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35113/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35113/1//COMMIT_MSG@9 PS1, Line 9: solder
soldered
Done
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35113 )
Change subject: mb/google/drallion: add dummy SPD file ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35113/2/src/mainboard/google/dralli... File src/mainboard/google/drallion/Kconfig:
https://review.coreboot.org/c/coreboot/+/35113/2/src/mainboard/google/dralli... PS2, Line 11: Will this change to SPD work with the Arcada and Sarien variants?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35113 )
Change subject: mb/google/drallion: add dummy SPD file ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35113/2/src/mainboard/google/dralli... File src/mainboard/google/drallion/Kconfig:
https://review.coreboot.org/c/coreboot/+/35113/2/src/mainboard/google/dralli... PS2, Line 11:
Will this change to SPD work with the Arcada and Sarien variants?
Yes, but no harm. I can boot with my Sarien. We read SPD from eeprom. I put the dummy as well.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35113 )
Change subject: mb/google/drallion: add dummy SPD file ......................................................................
Patch Set 2:
Patch Set 2:
(1 comment)
I think generic one is like dummy one. This will add Spd.bin in cbfs but useless. If we want add Spd into cbfs, we need remove this.
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35113 )
Change subject: mb/google/drallion: add dummy SPD file ......................................................................
Patch Set 2: Code-Review+2
Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35113 )
Change subject: mb/google/drallion: add dummy SPD file ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35113/2/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35113/2/src/mainboard/google/dralli... PS2, Line 17: SPD_SOURCES = empty_ddr4 # 0b00000 soldered down memory is not planned for arcada_cml and sarien_cml, do we really to update these 2 variants?
https://review.coreboot.org/c/coreboot/+/35113/2/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35113/2/src/mainboard/google/dralli... PS2, Line 17: 0b00000 soldered down memory is not planned for arcada_cml and sarien_cml, do we really to update these 2 variants?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35113 )
Change subject: mb/google/drallion: add dummy SPD file ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35113/2/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35113/2/src/mainboard/google/dralli... PS2, Line 17: 0b00000
soldered down memory is not planned for arcada_cml and sarien_cml, do we really to update these 2 va […]
same reason above.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35113 )
Change subject: mb/google/drallion: add dummy SPD file ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35113/2/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35113/2/src/mainboard/google/dralli... PS2, Line 17: SPD_SOURCES = empty_ddr4 # 0b00000
soldered down memory is not planned for arcada_cml and sarien_cml, do we really to update these 2 va […]
we need dummy one anyway.
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35113 )
Change subject: mb/google/drallion: add dummy SPD file ......................................................................
mb/google/drallion: add dummy SPD file
Drallion will use soldered down memory. Add dummy spd file.
BUG=b:139397313 BRANCH=N/A TEST=Build and check cbfs has the dummy spd.bin
Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220 Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35113 Reviewed-by: Mathew King mathewk@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/Makefile.inc A src/mainboard/google/drallion/spd/Makefile.inc A src/mainboard/google/drallion/spd/empty_ddr4.spd.hex M src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc 7 files changed, 77 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index cff56a4..2484ce7 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -8,7 +8,6 @@ select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_GOOGLE_WILCO - select GENERIC_SPD_BIN select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -19,7 +18,6 @@ select SOC_INTEL_COMETLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE - select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP select TPM2 select MAINBOARD_USES_IFD_EC_REGION diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc index c16e7d2..e7c90bb 100644 --- a/src/mainboard/google/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/Makefile.inc @@ -36,3 +36,5 @@
subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += spd diff --git a/src/mainboard/google/drallion/spd/Makefile.inc b/src/mainboard/google/drallion/spd/Makefile.inc new file mode 100644 index 0000000..e35544b --- /dev/null +++ b/src/mainboard/google/drallion/spd/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_BIN = $(obj)/spd.bin + +ifeq ($(SPD_SOURCES),) + SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) +else + SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +endif + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/drallion/spd/empty_ddr4.spd.hex b/src/mainboard/google/drallion/spd/empty_ddr4.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/google/drallion/spd/empty_ddr4.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc b/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc index 2bf028e..1cc010c 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc +++ b/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc @@ -13,6 +13,9 @@ ## GNU General Public License for more details. ##
+## GPP_F12-F16 indicates mem_id to match specific spd file +SPD_SOURCES = empty_ddr4 # 0b00000 + bootblock-y += gpio.c ramstage-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 2bf028e..0400d33 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -13,6 +13,9 @@ ## GNU General Public License for more details. ##
+## GPP_F12-F16 indicates mem_id to match specific spd file +SPD_SOURCES = empty_ddr4 # 0b00000 + bootblock-y += gpio.c ramstage-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc b/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc index 2bf028e..1cc010c 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc +++ b/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc @@ -13,6 +13,9 @@ ## GNU General Public License for more details. ##
+## GPP_F12-F16 indicates mem_id to match specific spd file +SPD_SOURCES = empty_ddr4 # 0b00000 + bootblock-y += gpio.c ramstage-y += gpio.c romstage-y += gpio.c
-
EricR Lai (Code Review) -
Mathew King (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
Selma Bensaid (Code Review)