Hello Varshit B Pandya,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/38849
to review the following change.
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
soc/intel/common: Update Jasperlake Device IDs
Update Jasperlake CPU, SA and PCH IDs
Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 22 files changed, 100 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38849/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e117ac2..cfd511e 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2809,8 +2809,6 @@ #define PCI_DEVICE_ID_INTEL_TGP_ESPI_24 0xA09D #define PCI_DEVICE_ID_INTEL_TGP_ESPI_25 0xA09E #define PCI_DEVICE_ID_INTEL_TGP_ESPI_26 0xA09F -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1 0x3887 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2 0x4d80 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_0 0x4b00 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_1 0x4b04 #define PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI 0x4b03 @@ -2819,6 +2817,7 @@ #define PCI_DEVICE_ID_INTEL_MCC_ESPI_2 0x4b05 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_3 0x4b06 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_4 0x4b07 +#define PCI_DEVICE_ID_INTEL_JSP_ESPI_7 0X4d87
/* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -3014,6 +3013,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14 0x02b5 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15 0x02b6 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16 0x02b7 + #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP1 0x06b8 #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP2 0x06b9 #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP3 0x06ba @@ -3038,14 +3038,15 @@ #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP22 0x06ad #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP23 0x06ae #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP24 0x06af -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1 0x38b8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2 0x38b9 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3 0x38ba -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4 0x38bb -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5 0x38bc -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6 0x38bd -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7 0x38be -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8 0x38bf + +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP1 0x4db8 +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP2 0x4db9 +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP3 0x4dba +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP4 0x4dbb +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP5 0x4dbc +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6 0x4dbd +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7 0x4dbe +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8 0x4dbf
#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1 0x4b38 #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2 0x4b39 @@ -3089,8 +3090,8 @@ #define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 #define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA 0x282a -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA 0x38d3 #define PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA 0x4b60 +#define PCI_DEVICE_ID_INTEL_JSP_SATA 0x4dd3
/* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -3106,8 +3107,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 #define PCI_DEVICE_ID_INTEL_CMP_H_PMC 0x06a1 #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC 0x38a1 #define PCI_DEVICE_ID_INTEL_MCC_PMC 0x4b21 +#define PCI_DEVICE_ID_INTEL_JSP_PMC 0x4da1
/* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3178,12 +3179,13 @@ #define PCI_DEVICE_ID_INTEL_MCC_I2C5 0x4b4c #define PCI_DEVICE_ID_INTEL_MCC_I2C6 0x4b44 #define PCI_DEVICE_ID_INTEL_MCC_I2C7 0x4b45 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0 0x38e8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1 0x38e9 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2 0x38ea -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3 0x38eb -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4 0x38c5 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5 0x38c6 + +#define PCI_DEVICE_ID_INTEL_JSP_I2C0 0x4de8 +#define PCI_DEVICE_ID_INTEL_JSP_I2C1 0x4de9 +#define PCI_DEVICE_ID_INTEL_JSP_I2C2 0x4dea +#define PCI_DEVICE_ID_INTEL_JSP_I2C3 0x4deb +#define PCI_DEVICE_ID_INTEL_JSP_I2C4 0x4dc5 +#define PCI_DEVICE_ID_INTEL_JSP_I2C5 0x4dc6
/* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 @@ -3224,9 +3226,9 @@ #define PCI_DEVICE_ID_INTEL_MCC_UART0 0x4b28 #define PCI_DEVICE_ID_INTEL_MCC_UART1 0x4b29 #define PCI_DEVICE_ID_INTEL_MCC_UART2 0x4b4d -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0 0x38a8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1 0x38a9 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2 0x38c7 +#define PCI_DEVICE_ID_INTEL_JSP_UART0 0x4da8 +#define PCI_DEVICE_ID_INTEL_JSP_UART1 0x4da9 +#define PCI_DEVICE_ID_INTEL_JSP_UART2 0x4dc7
/* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 @@ -3273,10 +3275,10 @@ #define PCI_DEVICE_ID_INTEL_MCC_GSPI0 0x4b2a #define PCI_DEVICE_ID_INTEL_MCC_GSPI1 0x4b2b #define PCI_DEVICE_ID_INTEL_MCC_GSPI2 0x4b37 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0 0x38aa -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1 0x38ab -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2 0x38fb -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI 0x38a4 +#define PCI_DEVICE_ID_INTEL_JSP_SPI0 0x4daa +#define PCI_DEVICE_ID_INTEL_JSP_SPI1 0x4dab +#define PCI_DEVICE_ID_INTEL_JSP_SPI2 0x4dfb +#define PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI 0x4da4
/* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 @@ -3387,7 +3389,10 @@ #define PCI_DEVICE_ID_INTEL_EHL_GT2_2 0x4550 #define PCI_DEVICE_ID_INTEL_EHL_GT1_3 0x4571 #define PCI_DEVICE_ID_INTEL_EHL_GT2_3 0x4570 -#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0 0x4569 +#define PCI_DEVICE_ID_INTEL_JSL_GT8 0x4E41 +#define PCI_DEVICE_ID_INTEL_JSL_GT16 0x4E51 +#define PCI_DEVICE_ID_INTEL_JSL_GT32 0x4E71 +#define PCI_DEVICE_ID_INTEL_JSL_NOGT 0x4E69
/* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3446,9 +3451,12 @@ #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 -#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 #define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510 +#define PCI_DEVICE_ID_INTEL_JSL_ID_Y 0x4510 +#define PCI_DEVICE_ID_INTEL_JSL_1 0x4532 +#define PCI_DEVICE_ID_INTEL_JSL_2 0x4518 +#define PCI_DEVICE_ID_INTEL_JSP_SA 0x4e22
/* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 @@ -3461,8 +3469,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 #define PCI_DEVICE_ID_INTEL_CMP_H_SMBUS 0x06a3 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS 0x38a3 #define PCI_DEVICE_ID_INTEL_MCC_SMBUS 0x4b23 +#define PCI_DEVICE_ID_INTEL_JSP_SMBUS 0x4da3
/* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3478,8 +3486,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed #define PCI_DEVICE_ID_INTEL_CMP_H_XHCI 0x06ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI 0x38ed #define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d +#define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded
/* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3495,8 +3503,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 #define PCI_DEVICE_ID_INTEL_CMP_H_P2SB 0x06a0 #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB 0x38a0 #define PCI_DEVICE_ID_INTEL_EHL_P2SB 0x4b20 +#define PCI_DEVICE_ID_INTEL_JSP_P2SB 0x4da0
/* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3507,8 +3515,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef #define PCI_DEVICE_ID_INTEL_CMP_H_SRAM 0x06ef #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM 0x38ef #define PCI_DEVICE_ID_INTEL_MCC_SRAM 0x4b7f +#define PCI_DEVICE_ID_INTEL_JSP_SRAM 0x4def
/* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -3525,8 +3533,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_H_AUDIO 0x06c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO 0x38c8 #define PCI_DEVICE_ID_INTEL_MCC_AUDIO 0x4b55 +#define PCI_DEVICE_ID_INTEL_JSP_AUDIO 0x4dc8
/* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -3544,11 +3552,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 #define PCI_DEVICE_ID_INTEL_CMP_H_CSE0 0x06e0 #define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0 0x38e0 #define PCI_DEVICE_ID_INTEL_MCC_CSE0 0x4b70 #define PCI_DEVICE_ID_INTEL_MCC_CSE1 0x4b71 #define PCI_DEVICE_ID_INTEL_MCC_CSE2 0x4b74 #define PCI_DEVICE_ID_INTEL_MCC_CSE3 0x4b75 +#define PCI_DEVICE_ID_INTEL_JSP_CSE0 0x4de0 +#define PCI_DEVICE_ID_INTEL_JSP_CSE1 0x4de1 +#define PCI_DEVICE_ID_INTEL_JSP_CSE2 0x4de4 +#define PCI_DEVICE_ID_INTEL_JSP_CSE3 0x4de5
/* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3561,6 +3572,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_H_XDCI 0x06ee #define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee #define PCI_DEVICE_ID_INTEL_MCC_XDCI 0x4b7e +#define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee
/* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca @@ -3571,12 +3583,13 @@ #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 #define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 #define PCI_DEVICE_ID_INTEL_CMP_H_SD 0x06f5 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD 0x38f8 #define PCI_DEVICE_ID_INTEL_MCC_SD 0x4b48 +#define PCI_DEVICE_ID_INTEL_JSP_SD 0x4df8
/* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b #define PCI_DEVICE_ID_INTEL_CMP_EMMC 0x02c4 +#define PCI_DEVICE_ID_INTEL_JSP_EMMC 0x4dc4
/* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 66a358f..62f2d1f 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -87,6 +87,7 @@ { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_JASPERLAKE}, { 0, 0 }, };
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index c82f3bd..9005266 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -756,11 +756,14 @@ PCI_DEVICE_ID_INTEL_CMP_CSE0, PCI_DEVICE_ID_INTEL_CMP_H_CSE0, PCI_DEVICE_ID_INTEL_TGL_CSE0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0, PCI_DEVICE_ID_INTEL_MCC_CSE0, PCI_DEVICE_ID_INTEL_MCC_CSE1, PCI_DEVICE_ID_INTEL_MCC_CSE2, PCI_DEVICE_ID_INTEL_MCC_CSE3, + PCI_DEVICE_ID_INTEL_JSP_CSE0, + PCI_DEVICE_ID_INTEL_JSP_CSE1, + PCI_DEVICE_ID_INTEL_JSP_CSE2, + PCI_DEVICE_ID_INTEL_JSP_CSE3, 0, };
diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 78f43a0..dc21b8e 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -36,8 +36,8 @@ PCI_DEVICE_ID_INTEL_CMP_H_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO, PCI_DEVICE_ID_INTEL_MCC_AUDIO, + PCI_DEVICE_ID_INTEL_JSP_AUDIO, 0, };
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 6c1436a..8d8445c 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -219,13 +219,16 @@ PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, - PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, PCI_DEVICE_ID_INTEL_EHL_GT1_1, PCI_DEVICE_ID_INTEL_EHL_GT2_1, PCI_DEVICE_ID_INTEL_EHL_GT1_2, PCI_DEVICE_ID_INTEL_EHL_GT2_2, PCI_DEVICE_ID_INTEL_EHL_GT1_3, PCI_DEVICE_ID_INTEL_EHL_GT2_3, + PCI_DEVICE_ID_INTEL_JSL_GT8, + PCI_DEVICE_ID_INTEL_JSL_GT16, + PCI_DEVICE_ID_INTEL_JSL_GT32, + PCI_DEVICE_ID_INTEL_JSL_NOGT, 0, };
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index ca854a9..57dad62 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -249,12 +249,6 @@ PCI_DEVICE_ID_INTEL_TGP_I2C5, PCI_DEVICE_ID_INTEL_TGP_I2C6, PCI_DEVICE_ID_INTEL_TGP_I2C7, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5, PCI_DEVICE_ID_INTEL_MCC_I2C0, PCI_DEVICE_ID_INTEL_MCC_I2C1, PCI_DEVICE_ID_INTEL_MCC_I2C2, @@ -263,6 +257,12 @@ PCI_DEVICE_ID_INTEL_MCC_I2C5, PCI_DEVICE_ID_INTEL_MCC_I2C6, PCI_DEVICE_ID_INTEL_MCC_I2C7, + PCI_DEVICE_ID_INTEL_JSP_I2C0, + PCI_DEVICE_ID_INTEL_JSP_I2C1, + PCI_DEVICE_ID_INTEL_JSP_I2C2, + PCI_DEVICE_ID_INTEL_JSP_I2C3, + PCI_DEVICE_ID_INTEL_JSP_I2C4, + PCI_DEVICE_ID_INTEL_JSP_I2C5, 0, };
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index c0c58af..5d32068 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -46,6 +46,7 @@ #define CPUID_COFFEELAKE_R0 0x906ed #define CPUID_ICELAKE_A0 0x706e0 #define CPUID_ICELAKE_B0 0x706e1 +#define CPUID_JASPERLAKE 0x906c0 #define CPUID_COMETLAKE_U_A0 0xa0660 #define CPUID_COMETLAKE_U_K0_S0 0xa0661 #define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index af90df6..8690e7c 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -231,8 +231,6 @@ PCI_DEVICE_ID_INTEL_TGP_ESPI_24, PCI_DEVICE_ID_INTEL_TGP_ESPI_25, PCI_DEVICE_ID_INTEL_TGP_ESPI_26, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, PCI_DEVICE_ID_INTEL_MCC_ESPI_0, PCI_DEVICE_ID_INTEL_MCC_ESPI_1, PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, @@ -241,6 +239,7 @@ PCI_DEVICE_ID_INTEL_MCC_ESPI_2, PCI_DEVICE_ID_INTEL_MCC_ESPI_3, PCI_DEVICE_ID_INTEL_MCC_ESPI_4, + PCI_DEVICE_ID_INTEL_JSP_ESPI_7, 0 };
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 34b6e06..89b5dd4 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -181,8 +181,8 @@ PCI_DEVICE_ID_INTEL_CMP_P2SB, PCI_DEVICE_ID_INTEL_CMP_H_P2SB, PCI_DEVICE_ID_INTEL_TGL_P2SB, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB, PCI_DEVICE_ID_INTEL_EHL_P2SB, + PCI_DEVICE_ID_INTEL_JSP_P2SB, 0, };
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index eab6667..cc20a48 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -290,14 +290,6 @@ PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP3, @@ -305,6 +297,14 @@ PCI_DEVICE_ID_INTEL_MCC_PCIE_RP5, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8, 0 };
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 3a9431b..ba64063 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -135,8 +135,8 @@ PCI_DEVICE_ID_INTEL_CMP_PMC, PCI_DEVICE_ID_INTEL_CMP_H_PMC, PCI_DEVICE_ID_INTEL_TGP_PMC, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC, PCI_DEVICE_ID_INTEL_MCC_PMC, + PCI_DEVICE_ID_INTEL_JSP_PMC, 0 };
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index cb12ad3..69e66d8 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -103,8 +103,8 @@ PCI_DEVICE_ID_INTEL_TGP_SATA, PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA, PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA, + PCI_DEVICE_ID_INTEL_JSP_SATA, 0 };
diff --git a/src/soc/intel/common/block/scs/mmc.c b/src/soc/intel/common/block/scs/mmc.c index 4ff3ac5..bbdde39 100644 --- a/src/soc/intel/common/block/scs/mmc.c +++ b/src/soc/intel/common/block/scs/mmc.c @@ -85,6 +85,7 @@
static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_EMMC, + PCI_DEVICE_ID_INTEL_JSP_EMMC, 0 };
diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 6b360d5..3f036e9 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -74,8 +74,8 @@ PCI_DEVICE_ID_INTEL_ICL_SD, PCI_DEVICE_ID_INTEL_CMP_SD, PCI_DEVICE_ID_INTEL_CMP_H_SD, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD, PCI_DEVICE_ID_INTEL_MCC_SD, + PCI_DEVICE_ID_INTEL_JSP_SD, 0 };
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 44b2165..d647cf8 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -97,8 +97,8 @@ PCI_DEVICE_ID_INTEL_CMP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_H_SMBUS, PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS, PCI_DEVICE_ID_INTEL_MCC_SMBUS, + PCI_DEVICE_ID_INTEL_JSP_SMBUS, 0 };
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 95981be..51ac697 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -93,14 +93,14 @@ PCI_DEVICE_ID_INTEL_TGP_GSPI4, PCI_DEVICE_ID_INTEL_TGP_GSPI5, PCI_DEVICE_ID_INTEL_TGP_GSPI6, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_MCC_SPI0, PCI_DEVICE_ID_INTEL_MCC_GSPI0, PCI_DEVICE_ID_INTEL_MCC_GSPI1, PCI_DEVICE_ID_INTEL_MCC_GSPI2, + PCI_DEVICE_ID_INTEL_JSP_SPI0, + PCI_DEVICE_ID_INTEL_JSP_SPI1, + PCI_DEVICE_ID_INTEL_JSP_SPI2, + PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI, 0 };
diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 6498d40..bfbacea 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -53,8 +53,8 @@ PCI_DEVICE_ID_INTEL_CMP_SRAM, PCI_DEVICE_ID_INTEL_CMP_H_SRAM, PCI_DEVICE_ID_INTEL_TGL_SRAM, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM, PCI_DEVICE_ID_INTEL_MCC_SRAM, + PCI_DEVICE_ID_INTEL_JSP_SRAM, 0, };
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 4c7d8c8..1f75534 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -399,9 +399,12 @@ PCI_DEVICE_ID_INTEL_TGL_ID_U, PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_Y, - PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, PCI_DEVICE_ID_INTEL_JSL_EHL, PCI_DEVICE_ID_INTEL_EHL_ID_1, + PCI_DEVICE_ID_INTEL_JSL_ID_Y, + PCI_DEVICE_ID_INTEL_JSL_1, + PCI_DEVICE_ID_INTEL_JSL_2, + PCI_DEVICE_ID_INTEL_JSP_SA, 0 };
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 08c0090..6f027e7 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -281,12 +281,12 @@ PCI_DEVICE_ID_INTEL_TGP_UART0, PCI_DEVICE_ID_INTEL_TGP_UART1, PCI_DEVICE_ID_INTEL_TGP_UART2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2, PCI_DEVICE_ID_INTEL_MCC_UART0, PCI_DEVICE_ID_INTEL_MCC_UART1, PCI_DEVICE_ID_INTEL_MCC_UART2, + PCI_DEVICE_ID_INTEL_JSP_UART0, + PCI_DEVICE_ID_INTEL_JSP_UART1, + PCI_DEVICE_ID_INTEL_JSP_UART2, 0, };
diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 5b70f9d..ff43201 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -46,6 +46,7 @@ PCI_DEVICE_ID_INTEL_CMP_H_XDCI, PCI_DEVICE_ID_INTEL_TGP_LP_XDCI, PCI_DEVICE_ID_INTEL_MCC_XDCI, + PCI_DEVICE_ID_INTEL_JSP_XDCI, 0 };
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 4b8a5cc..e4f98eb 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -133,8 +133,8 @@ PCI_DEVICE_ID_INTEL_CMP_LP_XHCI, PCI_DEVICE_ID_INTEL_CMP_H_XHCI, PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI, PCI_DEVICE_ID_INTEL_MCC_XHCI, + PCI_DEVICE_ID_INTEL_JSP_XHCI, 0 };
diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 127994d..3246219 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -38,6 +38,7 @@ const char *name; } cpu_table[] = { { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, + { CPUID_JASPERLAKE, "Jasperlake" }, };
static struct { @@ -47,7 +48,7 @@ { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, - { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, "Jasperlake Pre Prod" }, + { PCI_DEVICE_ID_INTEL_JSP_SA, "Jasperlake" }, { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, }; @@ -88,8 +89,7 @@ { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, "Jasperlake Pre Prod" }, - { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, "Jasperlake Pre Prod" }, + { PCI_DEVICE_ID_INTEL_JSP_ESPI_7, "Jasperlake PCH N" }, { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, @@ -105,7 +105,10 @@ { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, - { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, "Jasperlake Pre Prod GT0" }, + { PCI_DEVICE_ID_INTEL_JSL_NOGT, "Jasperlake A0 NO GT" }, + { PCI_DEVICE_ID_INTEL_JSL_GT8, "Jasperlake A0 GT1 (8 EU)" }, + { PCI_DEVICE_ID_INTEL_JSL_GT16, "Jasperlake A0 GT1 (16 EU)" }, + { PCI_DEVICE_ID_INTEL_JSL_GT32, "Jasperlake A0 GT1 (32 EU)" }, { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" }, { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" }, { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" },
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38849/1/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/38849/1/src/include/device/pci_ids.... PS1, Line 2820: #define PCI_DEVICE_ID_INTEL_JSP_ESPI_7 0X4d87 please, no space before tabs
Hello Patrick Rudolph, Sridhar Siricilla, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, Varshit B Pandya,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38849
to look at the new patch set (#2).
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
soc/intel/common: Update Jasperlake Device IDs
Update Jasperlake CPU, SA and PCH IDs
BUG=b:149185282 BRANCH=None TEST=Compilation for jasper lake board is working
Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 22 files changed, 100 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38849/2
Meera Ravindranath has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Removed reviewer Patrick Rudolph.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... PS5, Line 2820: 0X4d87
We are not planning to expose all the ESPI IDs in the header file. 0x4d87 is the only ID which […]
adding to above, Plan is to add on need basis, instead of listing all IDs, which may go unused.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38849/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38849/6//COMMIT_MSG@7 PS6, Line 7: Jasperlake Jasper Lake
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 6:
(5 comments)
Please mark the comments as resolved once done. That way All-Comments-Resolved gets checked.
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... PS5, Line 2820: 0X4d87
adding to above, Plan is to add on need basis, instead of listing all IDs, which may go unused.
Done
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... PS5, Line 3094: PCI_DEVICE_ID_INTEL_JSP_SATA
Done. Added the other SATA ID too. […]
Done
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... PS5, Line 3231: 0x4dc7
0x4dc7 is the correct one. We have raised a request to the EDS team. […]
Done
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... PS5, Line 3392: #define PCI_DEVICE_ID_INTEL_JSL_GT0 0x4E41
Done. Removed it. Thank you.
Done
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... PS5, Line 3453: #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 : #define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510
These are not applicable to JSP and are EHL specific. Only 0x4e22 holds good for JSP.
Done
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... PS5, Line 3394: JSL All the IDs use JSP and this ID uses JSL. Can you please keep it consistent with other IDs?
Also while you are at it, do you need to re-index GT1 to GT0 & GT2 to GT1. I am not an expert here. It is your call.
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... PS5, Line 3453: #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 : #define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510
Done
The confusion happened because of JSL_EHL. So I thought it has some relation with Jasper Lake. Can you please confirm that ID has got nothing to do with Jasper Lake.
Hello Patrick Rudolph, Karthik Ramasubramanian, Sridhar Siricilla, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, Varshit B Pandya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38849
to look at the new patch set (#7).
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
soc/intel/common: Update Jasperlake Device IDs
Update Jasperlake CPU, SA and PCH IDs.
BUG=b:149185282 BRANCH=None TEST=Compilation for jasper lake board is working
Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 22 files changed, 90 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38849/7
Hello Patrick Rudolph, Karthik Ramasubramanian, Sridhar Siricilla, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, Varshit B Pandya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38849
to look at the new patch set (#8).
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
soc/intel/common: Update Jasperlake Device IDs
Update Jasperlake CPU, SA and PCH IDs.
BUG=b:149185282 BRANCH=None TEST=Compilation for jasper lake board is working
Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 22 files changed, 90 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38849/8
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... PS5, Line 3394: JSL
All the IDs use JSP and this ID uses JSL. Can you please keep it consistent with other IDs? […]
The CPU core IPs use JSL and the PCH IPs use JSP. But thanks for the finding. Aligned the same naming for other CPU IPs too.
And we would like to index it as GT1 and GT2 only. Hope that is okay.
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... PS5, Line 3453: #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 : #define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510
The confusion happened because of JSL_EHL. So I thought it has some relation with Jasper Lake. […]
Yes, these IDs have got nothing to do with JasperLake. They are EHL specific.
Hello Patrick Rudolph, Karthik Ramasubramanian, Sridhar Siricilla, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, Varshit B Pandya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38849
to look at the new patch set (#9).
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
soc/intel/common: Update Jasperlake Device IDs
Update Jasperlake CPU, SA and PCH IDs.
BUG=b:149185282 BRANCH=None TEST=Compilation for jasper lake board is working
Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 22 files changed, 90 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38849/9
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38849/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38849/6//COMMIT_MSG@7 PS6, Line 7: Jasperlake
Jasper Lake
Please address this comment as well.
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... PS5, Line 3394: JSL
The CPU core IPs use JSL and the PCH IPs use JSP. But thanks for the finding. […]
Done
https://review.coreboot.org/c/coreboot/+/38849/5/src/include/device/pci_ids.... PS5, Line 3453: #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 : #define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510
Yes, these IDs have got nothing to do with JasperLake. They are EHL specific.
Done
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38849/9/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/38849/9/src/include/device/pci_ids.... PS9, Line 2820: JSL Isn't this part of PCH? If so, please use JSP here?
Hello Patrick Rudolph, Karthik Ramasubramanian, Sridhar Siricilla, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, Varshit B Pandya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38849
to look at the new patch set (#10).
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
soc/intel/common: Update Jasperlake Device IDs
Update Jasperlake CPU, SA and PCH IDs.
BUG=b:149185282 BRANCH=None TEST=Compilation for Jasper Lake board is working
Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 22 files changed, 90 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38849/10
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38849/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38849/6//COMMIT_MSG@7 PS6, Line 7: Jasperlake
Please address this comment as well.
Done
https://review.coreboot.org/c/coreboot/+/38849/9/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/38849/9/src/include/device/pci_ids.... PS9, Line 2820: JSL
Isn't this part of PCH? If so, please use JSP here?
Done
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 10:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38849/10/src/soc/intel/common/block... File src/soc/intel/common/block/cpu/mp_init.c:
https://review.coreboot.org/c/coreboot/+/38849/10/src/soc/intel/common/block... PS10, Line 90: CPUID_JASPERLAKE CPUID_JASPERLAKE_A0
https://review.coreboot.org/c/coreboot/+/38849/10/src/soc/intel/common/block... File src/soc/intel/common/block/include/intelblocks/mp_init.h:
https://review.coreboot.org/c/coreboot/+/38849/10/src/soc/intel/common/block... PS10, Line 49: CPUID_JASPERLAKE CPUID_JASPERLAKE_A0
https://review.coreboot.org/c/coreboot/+/38849/10/src/soc/intel/tigerlake/bo... File src/soc/intel/tigerlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/38849/10/src/soc/intel/tigerlake/bo... PS10, Line 41: Jasperlake Jasperlake A0
Hello Patrick Rudolph, Karthik Ramasubramanian, Sridhar Siricilla, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, Varshit B Pandya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38849
to look at the new patch set (#11).
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
soc/intel/common: Update Jasperlake Device IDs
Update Jasperlake CPU, SA and PCH IDs.
BUG=b:149185282 BRANCH=None TEST=Compilation for Jasper Lake board is working
Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 22 files changed, 90 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38849/11
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 11:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38849/10/src/soc/intel/common/block... File src/soc/intel/common/block/cpu/mp_init.c:
https://review.coreboot.org/c/coreboot/+/38849/10/src/soc/intel/common/block... PS10, Line 90: CPUID_JASPERLAKE
CPUID_JASPERLAKE_A0
Done
https://review.coreboot.org/c/coreboot/+/38849/10/src/soc/intel/common/block... File src/soc/intel/common/block/include/intelblocks/mp_init.h:
https://review.coreboot.org/c/coreboot/+/38849/10/src/soc/intel/common/block... PS10, Line 49: CPUID_JASPERLAKE
CPUID_JASPERLAKE_A0
Done
https://review.coreboot.org/c/coreboot/+/38849/10/src/soc/intel/tigerlake/bo... File src/soc/intel/tigerlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/38849/10/src/soc/intel/tigerlake/bo... PS10, Line 41: Jasperlake
Jasperlake A0
Done
Hello Patrick Rudolph, Karthik Ramasubramanian, Sridhar Siricilla, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, Varshit B Pandya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38849
to look at the new patch set (#12).
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
soc/intel/common: Update Jasperlake Device IDs
Update Jasperlake CPU, SA and PCH IDs.
BUG=b:149185282 BRANCH=None TEST=Compilation for Jasper Lake board is working
Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 22 files changed, 90 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38849/12
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 12: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38849/12//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38849/12//COMMIT_MSG@7 PS12, Line 7: Jasperlake Jasper Lake
https://review.coreboot.org/c/coreboot/+/38849/12//COMMIT_MSG@9 PS12, Line 9: Jasperlake Jasper Lake
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasperlake Device IDs ......................................................................
Patch Set 12: Code-Review+1
Hello Patrick Rudolph, Karthik Ramasubramanian, Sridhar Siricilla, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Rizwan Qureshi, Varshit B Pandya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38849
to look at the new patch set (#13).
Change subject: soc/intel/common: Update Jasper Lake Device IDs ......................................................................
soc/intel/common: Update Jasper Lake Device IDs
Update Jasper Lake CPU, SA and PCH IDs.
BUG=b:149185282 BRANCH=None TEST=Compilation for Jasper Lake board is working
Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 22 files changed, 90 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38849/13
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasper Lake Device IDs ......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38849/12//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38849/12//COMMIT_MSG@7 PS12, Line 7: Jasperlake
Jasper Lake
Done
https://review.coreboot.org/c/coreboot/+/38849/12//COMMIT_MSG@9 PS12, Line 9: Jasperlake
Jasper Lake
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38849 )
Change subject: soc/intel/common: Update Jasper Lake Device IDs ......................................................................
soc/intel/common: Update Jasper Lake Device IDs
Update Jasper Lake CPU, SA and PCH IDs.
BUG=b:149185282 BRANCH=None TEST=Compilation for Jasper Lake board is working
Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38849 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aamir Bohra aamir.bohra@intel.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/tigerlake/bootblock/report_platform.c 22 files changed, 90 insertions(+), 72 deletions(-)
Approvals: build bot (Jenkins): Verified Aamir Bohra: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c6602c4..47b1825 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2809,8 +2809,6 @@ #define PCI_DEVICE_ID_INTEL_TGP_ESPI_24 0xA09D #define PCI_DEVICE_ID_INTEL_TGP_ESPI_25 0xA09E #define PCI_DEVICE_ID_INTEL_TGP_ESPI_26 0xA09F -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1 0x3887 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2 0x4d80 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_0 0x4b00 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_1 0x4b04 #define PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI 0x4b03 @@ -2819,6 +2817,7 @@ #define PCI_DEVICE_ID_INTEL_MCC_ESPI_2 0x4b05 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_3 0x4b06 #define PCI_DEVICE_ID_INTEL_MCC_ESPI_4 0x4b07 +#define PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI 0X4d87
/* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -3014,6 +3013,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14 0x02b5 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15 0x02b6 #define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16 0x02b7 + #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP1 0x06b8 #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP2 0x06b9 #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP3 0x06ba @@ -3038,14 +3038,15 @@ #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP22 0x06ad #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP23 0x06ae #define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP24 0x06af -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1 0x38b8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2 0x38b9 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3 0x38ba -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4 0x38bb -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5 0x38bc -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6 0x38bd -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7 0x38be -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8 0x38bf + +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP1 0x4db8 +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP2 0x4db9 +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP3 0x4dba +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP4 0x4dbb +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP5 0x4dbc +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6 0x4dbd +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7 0x4dbe +#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8 0x4dbf
#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1 0x4b38 #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2 0x4b39 @@ -3089,8 +3090,9 @@ #define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5 #define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 #define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA 0x282a -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA 0x38d3 #define PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA 0x4b60 +#define PCI_DEVICE_ID_INTEL_JSP_SATA_1 0x4dd2 +#define PCI_DEVICE_ID_INTEL_JSP_SATA_2 0x4dd3
/* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -3106,8 +3108,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 #define PCI_DEVICE_ID_INTEL_CMP_H_PMC 0x06a1 #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC 0x38a1 #define PCI_DEVICE_ID_INTEL_MCC_PMC 0x4b21 +#define PCI_DEVICE_ID_INTEL_JSP_PMC 0x4da1
/* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3178,12 +3180,13 @@ #define PCI_DEVICE_ID_INTEL_MCC_I2C5 0x4b4c #define PCI_DEVICE_ID_INTEL_MCC_I2C6 0x4b44 #define PCI_DEVICE_ID_INTEL_MCC_I2C7 0x4b45 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0 0x38e8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1 0x38e9 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2 0x38ea -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3 0x38eb -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4 0x38c5 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5 0x38c6 + +#define PCI_DEVICE_ID_INTEL_JSP_I2C0 0x4de8 +#define PCI_DEVICE_ID_INTEL_JSP_I2C1 0x4de9 +#define PCI_DEVICE_ID_INTEL_JSP_I2C2 0x4dea +#define PCI_DEVICE_ID_INTEL_JSP_I2C3 0x4deb +#define PCI_DEVICE_ID_INTEL_JSP_I2C4 0x4dc5 +#define PCI_DEVICE_ID_INTEL_JSP_I2C5 0x4dc6
/* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 @@ -3224,9 +3227,9 @@ #define PCI_DEVICE_ID_INTEL_MCC_UART0 0x4b28 #define PCI_DEVICE_ID_INTEL_MCC_UART1 0x4b29 #define PCI_DEVICE_ID_INTEL_MCC_UART2 0x4b4d -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0 0x38a8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1 0x38a9 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2 0x38c7 +#define PCI_DEVICE_ID_INTEL_JSP_UART0 0x4da8 +#define PCI_DEVICE_ID_INTEL_JSP_UART1 0x4da9 +#define PCI_DEVICE_ID_INTEL_JSP_UART2 0x4dc7
/* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 @@ -3273,10 +3276,10 @@ #define PCI_DEVICE_ID_INTEL_MCC_GSPI0 0x4b2a #define PCI_DEVICE_ID_INTEL_MCC_GSPI1 0x4b2b #define PCI_DEVICE_ID_INTEL_MCC_GSPI2 0x4b37 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0 0x38aa -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1 0x38ab -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2 0x38fb -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI 0x38a4 +#define PCI_DEVICE_ID_INTEL_JSP_SPI0 0x4daa +#define PCI_DEVICE_ID_INTEL_JSP_SPI1 0x4dab +#define PCI_DEVICE_ID_INTEL_JSP_SPI2 0x4dfb +#define PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI 0x4da4
/* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 @@ -3387,7 +3390,8 @@ #define PCI_DEVICE_ID_INTEL_EHL_GT2_2 0x4550 #define PCI_DEVICE_ID_INTEL_EHL_GT1_3 0x4571 #define PCI_DEVICE_ID_INTEL_EHL_GT2_3 0x4570 -#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0 0x4569 +#define PCI_DEVICE_ID_INTEL_JSL_GT1 0x4E51 +#define PCI_DEVICE_ID_INTEL_JSL_GT2 0x4E71
/* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3447,9 +3451,9 @@ #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 -#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 #define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510 +#define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22
/* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 @@ -3462,8 +3466,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 #define PCI_DEVICE_ID_INTEL_CMP_H_SMBUS 0x06a3 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS 0x38a3 #define PCI_DEVICE_ID_INTEL_MCC_SMBUS 0x4b23 +#define PCI_DEVICE_ID_INTEL_JSP_SMBUS 0x4da3
/* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3479,8 +3483,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed #define PCI_DEVICE_ID_INTEL_CMP_H_XHCI 0x06ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI 0x38ed #define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d +#define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded
/* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3496,8 +3500,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 #define PCI_DEVICE_ID_INTEL_CMP_H_P2SB 0x06a0 #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB 0x38a0 #define PCI_DEVICE_ID_INTEL_EHL_P2SB 0x4b20 +#define PCI_DEVICE_ID_INTEL_JSP_P2SB 0x4da0
/* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3508,8 +3512,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef #define PCI_DEVICE_ID_INTEL_CMP_H_SRAM 0x06ef #define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM 0x38ef #define PCI_DEVICE_ID_INTEL_MCC_SRAM 0x4b7f +#define PCI_DEVICE_ID_INTEL_JSP_SRAM 0x4def
/* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -3526,8 +3530,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_H_AUDIO 0x06c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 #define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO 0x38c8 #define PCI_DEVICE_ID_INTEL_MCC_AUDIO 0x4b55 +#define PCI_DEVICE_ID_INTEL_JSP_AUDIO 0x4dc8
/* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -3545,11 +3549,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 #define PCI_DEVICE_ID_INTEL_CMP_H_CSE0 0x06e0 #define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0 0x38e0 #define PCI_DEVICE_ID_INTEL_MCC_CSE0 0x4b70 #define PCI_DEVICE_ID_INTEL_MCC_CSE1 0x4b71 #define PCI_DEVICE_ID_INTEL_MCC_CSE2 0x4b74 #define PCI_DEVICE_ID_INTEL_MCC_CSE3 0x4b75 +#define PCI_DEVICE_ID_INTEL_JSP_CSE0 0x4de0 +#define PCI_DEVICE_ID_INTEL_JSP_CSE1 0x4de1 +#define PCI_DEVICE_ID_INTEL_JSP_CSE2 0x4de4 +#define PCI_DEVICE_ID_INTEL_JSP_CSE3 0x4de5
/* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3562,6 +3569,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_H_XDCI 0x06ee #define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee #define PCI_DEVICE_ID_INTEL_MCC_XDCI 0x4b7e +#define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee
/* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca @@ -3572,12 +3580,13 @@ #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 #define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 #define PCI_DEVICE_ID_INTEL_CMP_H_SD 0x06f5 -#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD 0x38f8 #define PCI_DEVICE_ID_INTEL_MCC_SD 0x4b48 +#define PCI_DEVICE_ID_INTEL_JSP_SD 0x4df8
/* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b #define PCI_DEVICE_ID_INTEL_CMP_EMMC 0x02c4 +#define PCI_DEVICE_ID_INTEL_JSP_EMMC 0x4dc4
/* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 66a358f..87cebc0 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -87,6 +87,7 @@ { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0_P1 }, { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0}, { 0, 0 }, };
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 5877d53..48c26f3 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -791,11 +791,14 @@ PCI_DEVICE_ID_INTEL_CMP_CSE0, PCI_DEVICE_ID_INTEL_CMP_H_CSE0, PCI_DEVICE_ID_INTEL_TGL_CSE0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0, PCI_DEVICE_ID_INTEL_MCC_CSE0, PCI_DEVICE_ID_INTEL_MCC_CSE1, PCI_DEVICE_ID_INTEL_MCC_CSE2, PCI_DEVICE_ID_INTEL_MCC_CSE3, + PCI_DEVICE_ID_INTEL_JSP_CSE0, + PCI_DEVICE_ID_INTEL_JSP_CSE1, + PCI_DEVICE_ID_INTEL_JSP_CSE2, + PCI_DEVICE_ID_INTEL_JSP_CSE3, 0, };
diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 78f43a0..dc21b8e 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -36,8 +36,8 @@ PCI_DEVICE_ID_INTEL_CMP_H_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_TGL_AUDIO, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO, PCI_DEVICE_ID_INTEL_MCC_AUDIO, + PCI_DEVICE_ID_INTEL_JSP_AUDIO, 0, };
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 6c1436a..29d6c53 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -219,13 +219,14 @@ PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, - PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, PCI_DEVICE_ID_INTEL_EHL_GT1_1, PCI_DEVICE_ID_INTEL_EHL_GT2_1, PCI_DEVICE_ID_INTEL_EHL_GT1_2, PCI_DEVICE_ID_INTEL_EHL_GT2_2, PCI_DEVICE_ID_INTEL_EHL_GT1_3, PCI_DEVICE_ID_INTEL_EHL_GT2_3, + PCI_DEVICE_ID_INTEL_JSL_GT1, + PCI_DEVICE_ID_INTEL_JSL_GT2, 0, };
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index ca854a9..57dad62 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -249,12 +249,6 @@ PCI_DEVICE_ID_INTEL_TGP_I2C5, PCI_DEVICE_ID_INTEL_TGP_I2C6, PCI_DEVICE_ID_INTEL_TGP_I2C7, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5, PCI_DEVICE_ID_INTEL_MCC_I2C0, PCI_DEVICE_ID_INTEL_MCC_I2C1, PCI_DEVICE_ID_INTEL_MCC_I2C2, @@ -263,6 +257,12 @@ PCI_DEVICE_ID_INTEL_MCC_I2C5, PCI_DEVICE_ID_INTEL_MCC_I2C6, PCI_DEVICE_ID_INTEL_MCC_I2C7, + PCI_DEVICE_ID_INTEL_JSP_I2C0, + PCI_DEVICE_ID_INTEL_JSP_I2C1, + PCI_DEVICE_ID_INTEL_JSP_I2C2, + PCI_DEVICE_ID_INTEL_JSP_I2C3, + PCI_DEVICE_ID_INTEL_JSP_I2C4, + PCI_DEVICE_ID_INTEL_JSP_I2C5, 0, };
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index c0c58af..4c528e0 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -46,6 +46,7 @@ #define CPUID_COFFEELAKE_R0 0x906ed #define CPUID_ICELAKE_A0 0x706e0 #define CPUID_ICELAKE_B0 0x706e1 +#define CPUID_JASPERLAKE_A0 0x906c0 #define CPUID_COMETLAKE_U_A0 0xa0660 #define CPUID_COMETLAKE_U_K0_S0 0xa0661 #define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index af90df6..3524a8f 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -231,8 +231,6 @@ PCI_DEVICE_ID_INTEL_TGP_ESPI_24, PCI_DEVICE_ID_INTEL_TGP_ESPI_25, PCI_DEVICE_ID_INTEL_TGP_ESPI_26, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, PCI_DEVICE_ID_INTEL_MCC_ESPI_0, PCI_DEVICE_ID_INTEL_MCC_ESPI_1, PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, @@ -241,6 +239,7 @@ PCI_DEVICE_ID_INTEL_MCC_ESPI_2, PCI_DEVICE_ID_INTEL_MCC_ESPI_3, PCI_DEVICE_ID_INTEL_MCC_ESPI_4, + PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, 0 };
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index c968409..5b72e72 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -155,8 +155,8 @@ PCI_DEVICE_ID_INTEL_CMP_P2SB, PCI_DEVICE_ID_INTEL_CMP_H_P2SB, PCI_DEVICE_ID_INTEL_TGL_P2SB, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB, PCI_DEVICE_ID_INTEL_EHL_P2SB, + PCI_DEVICE_ID_INTEL_JSP_P2SB, 0, };
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index eab6667..cc20a48 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -290,14 +290,6 @@ PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP3, @@ -305,6 +297,14 @@ PCI_DEVICE_ID_INTEL_MCC_PCIE_RP5, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6, PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8, 0 };
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 3a9431b..ba64063 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -135,8 +135,8 @@ PCI_DEVICE_ID_INTEL_CMP_PMC, PCI_DEVICE_ID_INTEL_CMP_H_PMC, PCI_DEVICE_ID_INTEL_TGP_PMC, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC, PCI_DEVICE_ID_INTEL_MCC_PMC, + PCI_DEVICE_ID_INTEL_JSP_PMC, 0 };
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index cb12ad3..5439767 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -103,8 +103,9 @@ PCI_DEVICE_ID_INTEL_TGP_SATA, PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA, PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA, + PCI_DEVICE_ID_INTEL_JSP_SATA_1, + PCI_DEVICE_ID_INTEL_JSP_SATA_2, 0 };
diff --git a/src/soc/intel/common/block/scs/mmc.c b/src/soc/intel/common/block/scs/mmc.c index 4ff3ac5..bbdde39 100644 --- a/src/soc/intel/common/block/scs/mmc.c +++ b/src/soc/intel/common/block/scs/mmc.c @@ -85,6 +85,7 @@
static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_EMMC, + PCI_DEVICE_ID_INTEL_JSP_EMMC, 0 };
diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 6b360d5..3f036e9 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -74,8 +74,8 @@ PCI_DEVICE_ID_INTEL_ICL_SD, PCI_DEVICE_ID_INTEL_CMP_SD, PCI_DEVICE_ID_INTEL_CMP_H_SD, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD, PCI_DEVICE_ID_INTEL_MCC_SD, + PCI_DEVICE_ID_INTEL_JSP_SD, 0 };
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 44b2165..d647cf8 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -97,8 +97,8 @@ PCI_DEVICE_ID_INTEL_CMP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_H_SMBUS, PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS, PCI_DEVICE_ID_INTEL_MCC_SMBUS, + PCI_DEVICE_ID_INTEL_JSP_SMBUS, 0 };
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 95981be..51ac697 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -93,14 +93,14 @@ PCI_DEVICE_ID_INTEL_TGP_GSPI4, PCI_DEVICE_ID_INTEL_TGP_GSPI5, PCI_DEVICE_ID_INTEL_TGP_GSPI6, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_MCC_SPI0, PCI_DEVICE_ID_INTEL_MCC_GSPI0, PCI_DEVICE_ID_INTEL_MCC_GSPI1, PCI_DEVICE_ID_INTEL_MCC_GSPI2, + PCI_DEVICE_ID_INTEL_JSP_SPI0, + PCI_DEVICE_ID_INTEL_JSP_SPI1, + PCI_DEVICE_ID_INTEL_JSP_SPI2, + PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI, 0 };
diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 6498d40..bfbacea 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -53,8 +53,8 @@ PCI_DEVICE_ID_INTEL_CMP_SRAM, PCI_DEVICE_ID_INTEL_CMP_H_SRAM, PCI_DEVICE_ID_INTEL_TGL_SRAM, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM, PCI_DEVICE_ID_INTEL_MCC_SRAM, + PCI_DEVICE_ID_INTEL_JSP_SRAM, 0, };
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e660dbf..02a6788 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -400,9 +400,9 @@ PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, PCI_DEVICE_ID_INTEL_TGL_ID_Y, - PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, PCI_DEVICE_ID_INTEL_JSL_EHL, PCI_DEVICE_ID_INTEL_EHL_ID_1, + PCI_DEVICE_ID_INTEL_JSL_ID_1, 0 };
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 08c0090..6f027e7 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -281,12 +281,12 @@ PCI_DEVICE_ID_INTEL_TGP_UART0, PCI_DEVICE_ID_INTEL_TGP_UART1, PCI_DEVICE_ID_INTEL_TGP_UART2, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2, PCI_DEVICE_ID_INTEL_MCC_UART0, PCI_DEVICE_ID_INTEL_MCC_UART1, PCI_DEVICE_ID_INTEL_MCC_UART2, + PCI_DEVICE_ID_INTEL_JSP_UART0, + PCI_DEVICE_ID_INTEL_JSP_UART1, + PCI_DEVICE_ID_INTEL_JSP_UART2, 0, };
diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 5b70f9d..ff43201 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -46,6 +46,7 @@ PCI_DEVICE_ID_INTEL_CMP_H_XDCI, PCI_DEVICE_ID_INTEL_TGP_LP_XDCI, PCI_DEVICE_ID_INTEL_MCC_XDCI, + PCI_DEVICE_ID_INTEL_JSP_XDCI, 0 };
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 4b8a5cc..e4f98eb 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -133,8 +133,8 @@ PCI_DEVICE_ID_INTEL_CMP_LP_XHCI, PCI_DEVICE_ID_INTEL_CMP_H_XHCI, PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, - PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI, PCI_DEVICE_ID_INTEL_MCC_XHCI, + PCI_DEVICE_ID_INTEL_JSP_XHCI, 0 };
diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index f38e9cf..c6a62c3 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -38,6 +38,7 @@ const char *name; } cpu_table[] = { { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, + { CPUID_JASPERLAKE_A0, "Jasperlake A0" }, };
static struct { @@ -48,7 +49,7 @@ { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, - { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, "Jasperlake Pre Prod" }, + { PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake-1" }, { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, }; @@ -89,8 +90,7 @@ { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1, "Jasperlake Pre Prod" }, - { PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2, "Jasperlake Pre Prod" }, + { PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, "Jasperlake Super" }, { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, @@ -106,7 +106,8 @@ { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, - { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0, "Jasperlake Pre Prod GT0" }, + { PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" }, + { PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" }, { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" }, { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" }, { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" },
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