[M] Change in coreboot[master]: device: Clear lane error status

[Wilson Chou (Code Review)]

Attention is currently required from: Wilson Chou, Marc Jones, Jonathan Zhang, Ryback Hung, Johnny Lin, Paul Menzel, Tim Wawrzynczak, Shuming Chu (Shuming).

Hello build bot (Jenkins), Marc Jones, Jonathan Zhang, Ryback Hung, Johnny Lin, Shuming Chu (Shuming),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/67264

to look at the new patch set (#4).

Change subject: device: Clear lane error status
......................................................................

device: Clear lane error status

Refer to PCI Express Base rev6.0 v1.0, 4.2.7 Link Training and Status
State Rules, Lane Error Status is normal to record the error when link
training. To make sure Lane Error Status is correct in OS runtime,
add a Kconfig PCIEXP_LANE_ERR_STAT_CLEAR that clears the PCIe lane error
status register at the end of PCIe link training.

Test=On Crater Lake, lspci -vvv shows
bb:01.0 PCI bridge: Intel Corporation Device 352a (rev 03)
(prog-if 00 [Normal decode])
Capabilities: [a30 v1] Secondary PCI Express
    LnkCtl3: LnkEquIntrruptEn- PerformEqu-
    LaneErrStat: LaneErr at lane: 0

Signed-off-by: Wilson Chou 
Change-Id: I6344223636409d8fc25e365a6375fc81e69f41a5
---
M src/device/Kconfig
M src/device/pciexp_device.c
M src/include/device/pci_def.h
3 files changed, 59 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/67264/4