Change in coreboot[master]: soc/intel/common/block: Add Intel common UART code

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18952 )

Change subject: soc/intel/common/block: Add Intel common UART code
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Patch Set 7:

(4 comments)

https://review.coreboot.org/#/c/18952/7/src/soc/intel/common/block/include/i...
File src/soc/intel/common/block/include/intelblocks/uart.h:

PS7, Line 4: Copyright 2017 Intel Corporation.
header issue

PS7, Line 21: soc_uart_init
common code shouldn't have anything like "soc"

https://review.coreboot.org/#/c/18952/7/src/soc/intel/common/block/uart/uart...
File src/soc/intel/common/block/uart/uart.c:

PS7, Line 20: device_t dev
can't we have dev as local

PS7, Line 33: 	/* Take UART out of reset */
            : 	write32(base + LPSS_RESET_CTL_REG, LPSS_CNT_RST_RELEASE);
            : 
            : 	/* Set M and N divisor inputs and enable clock */
            : 	clk_sel = LPSS_CLOCK_DIV_N(clk_n_val) | LPSS_CLOCK_DIV_M(clk_m_val);
            : 	write32(base + LPSS_CLOCK_CTL_REG, clk_sel | LPSS_CNT_CLK_UPDATE);
            : 	write32(base + LPSS_CLOCK_CTL_REG, clk_sel | LPSS_CNT_CLOCK_EN);
> Aren't these generic to all lpss blocks? including i2c and spi as well? If

lets create a LPSS.c with a common LPSS block. then from i2c an spi, just API call