Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50462 )
Change subject: soc/amd: factor out common SMM relocation code ......................................................................
soc/amd: factor out common SMM relocation code
The common code gets moved to soc/amd/common/block/cpu/smm, since it is related to the CPU cores and soc/amd/common/block/smi is about the SMI/ SCI functionality in the FCH part. Also relocation_handler gets renamed to smm_relocation_handler to keep it clear what it does, since it got moved to another compilation unit.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/cpu/Kconfig A src/soc/amd/common/block/cpu/smm/Makefile.inc A src/soc/amd/common/block/cpu/smm/smm_relocate.c A src/soc/amd/common/block/include/amdblocks/smm.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/cpu.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/cpu.c 9 files changed, 79 insertions(+), 96 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/50462/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 6e844c2..7bd9873 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -31,6 +31,7 @@ select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SMM select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SSE2 diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index c155975..996605e 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -28,6 +28,12 @@
endif # SOC_AMD_COMMON_BLOCK_NONCAR
+config SOC_AMD_COMMON_BLOCK_SMM + bool + default n + help + Add common SMM relocation and handler functionality to the build. + config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H bool select COLLECT_TIMESTAMPS_NO_TSC # selected use SoC-specific timestamp function diff --git a/src/soc/amd/common/block/cpu/smm/Makefile.inc b/src/soc/amd/common/block/cpu/smm/Makefile.inc new file mode 100644 index 0000000..0639890 --- /dev/null +++ b/src/soc/amd/common/block/cpu/smm/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMM),y) + +ramstage-y += smm_relocate.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c new file mode 100644 index 0000000..1d7cc68 --- /dev/null +++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/smm.h> +#include <console/console.h> +#include <cpu/amd/amd64_save_state.h> +#include <cpu/amd/msr.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> +#include <types.h> + +static struct smm_relocation_params smm_reloc_params; + +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + smm_region(&tseg_base, &tseg_size); + + params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB); + params->tseg_base.hi = 0; + params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB); + params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); + + params->tseg_mask.lo |= SMM_TSEG_WB; +} + +void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); +} + +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) +{ + struct smm_relocation_params *relo_params = &smm_reloc_params; + amd64_smm_state_save_area_t *smm_state; + + wrmsr(SMM_ADDR_MSR, relo_params->tseg_base); + wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); + + smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); + smm_state->smbase = staggered_smbase; +} diff --git a/src/soc/amd/common/block/include/amdblocks/smm.h b/src/soc/amd/common/block/include/amdblocks/smm.h new file mode 100644 index 0000000..0fbef42 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/smm.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/msr.h> +#include <types.h> + +struct smm_relocation_params { + msr_t tseg_base; + msr_t tseg_mask; +}; + +void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4868d84..f504d09 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -42,6 +42,7 @@ select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SMM select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 8ee065d..088660e 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/cpu.h> +#include <amdblocks/smm.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/amd/msr.h> -#include <cpu/amd/amd64_save_state.h> #include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> @@ -22,12 +21,6 @@ /* * MP and SMM loading initialization. */ -struct smm_relocation_params { - msr_t tseg_base; - msr_t tseg_mask; -}; - -static struct smm_relocation_params smm_reloc_params;
/* * Do essential initialization tasks before APs can be fired up - @@ -42,45 +35,6 @@ x86_mtrr_check(); }
-static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - smm_region(&tseg_base, &tseg_size); - - params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB); - params->tseg_base.hi = 0; - params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB); - params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); - - params->tseg_mask.lo |= SMM_TSEG_WB; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); -} - -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - amd64_smm_state_save_area_t *smm_state; - - wrmsr(SMM_ADDR_MSR, relo_params->tseg_base); - wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); - - smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - static void post_mp_init(void) { global_smi_enable(); @@ -91,7 +45,7 @@ .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, - .relocation_handler = relocation_handler, + .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, };
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b400e1b..728e063 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -41,6 +41,7 @@ select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SMM select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_UART select SSE2 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 9992fc5..badea8b 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/smm.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/amd/msr.h> -#include <cpu/amd/amd64_save_state.h> #include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> @@ -21,12 +20,6 @@ /* * MP and SMM loading initialization. */ -struct smm_relocation_params { - msr_t tseg_base; - msr_t tseg_mask; -}; - -static struct smm_relocation_params smm_reloc_params;
/* * Do essential initialization tasks before APs can be fired up - @@ -47,50 +40,11 @@ + 1; }
-static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - smm_region(&tseg_base, &tseg_size); - - params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB); - params->tseg_base.hi = 0; - params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB); - params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); - - params->tseg_mask.lo |= SMM_TSEG_WB; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); -} - -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - amd64_smm_state_save_area_t *smm_state; - - wrmsr(SMM_ADDR_MSR, relo_params->tseg_base); - wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); - - smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, - .relocation_handler = relocation_handler, + .relocation_handler = smm_relocation_handler, .post_mp_init = global_smi_enable, };
-
Felix Held (Code Review)