[S] Change in coreboot[main]: mb/google/brox: Check to powergate the UFS controller

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86151?usp=email )

Change subject: mb/google/brox: Check to powergate the UFS controller
......................................................................

mb/google/brox: Check to powergate the UFS controller

On boards with non-UFS storage, during certain kind of resets UFS
controller is not powergated even though it is disabled. This leads to
suspend/resume failures during that boot cycle. UFS controller is always
disabled in romstage. If the UFS controller is disabled in devicetree
and is not powergated, then trigger an extra reset for UFS disablement
to take effect.

BUG=b:391449110
TEST=Build Brox BIOS image and boot to OS. Ensure that when the device
switches from normal mode to developer mode.

Change-Id: I31f1cfc995a98bb345ac64ec3ae68a3bcc413f29
---
M src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
R src/mainboard/google/brox/variants/baseboard/brox/reset_check.c
3 files changed, 46 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/86151/1

diff --git a/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk b/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk
index b3149ba..eb8625d 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk
+++ b/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk
@@ -4,10 +4,11 @@

romstage-y += memory.c
 romstage-y += gpio.c
-romstage-y += romstage.c
+romstage-y += reset_check.c
 romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads

ramstage-y += gpio.c
 ramstage-y += ramstage.c
+ramstage-y += reset_check.c

smm-$(CONFIG_SMMSTORE) += gpio.c
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
index f079d7a..3ac9dbd 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
@@ -2,11 +2,14 @@

#include <acpi/acpi_device.h>
 #include <baseboard/variants.h>
+#include <bootstate.h>
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <drivers/intel/dptf/chip.h>
 #include <ec/google/chromeec/ec.h>
 #include <intelblocks/power_limit.h>
+#include <intelblocks/pmclib.h>
 #include <soc/pci_devs.h>
 #include <static.h>

@@ -100,3 +103,44 @@
    	settings->pl1.min_power, settings->pl1.max_power, settings->pl2.min_power,
    	settings->pl2.max_power, soc_config->tdp_pl4);
 }
+
+#define PMC_PCH_ISH_IP_PG_STS_OFFSET 0x1D92
+#define ISH_PG_STS BIT(1)
+
+#define PMC_PCH_UFS0_IP_PG_STS_OFFSET 0x1D96
+#define UFS0_PG_STS BIT(4)
+
+extern bool mainboard_expects_another_reset(void);
+
+static uint8_t pmc_get_pch_ip_pg_sts(uint32_t offset)
+{
+	uint8_t val = 0;
+	uintptr_t pmc_bar;
+
+	pmc_bar = soc_read_pmc_base();
+	val = read8p(pmc_bar + offset);
+	return val;
+}
+
+static bool is_ish_and_ufs_powergated(void)
+{
+	uint8_t ish_pg_sts = pmc_get_pch_ip_pg_sts(PMC_PCH_ISH_IP_PG_STS_OFFSET);
+	uint8_t ufs0_pg_sts = pmc_get_pch_ip_pg_sts(PMC_PCH_UFS0_IP_PG_STS_OFFSET);
+
+	printk(BIOS_INFO, "ISH Status: 0x%02x, UFS0 Status: 0x%02x\n", ish_pg_sts, ufs0_pg_sts);
+	if ((ish_pg_sts & ISH_PG_STS) && (ufs0_pg_sts & UFS0_PG_STS))
+		return true;
+	return false;
+}
+
+static void recheck_ufs_state(void *unused)
+{
+	if (!is_devfn_enabled(PCH_DEVFN_UFS) && !is_ish_and_ufs_powergated()) {
+		printk(BIOS_ERR, "ISH and/or UFS not powergated.\n");
+		if (!mainboard_expects_another_reset()) {
+			printk(BIOS_INFO, "Triggering warm reset to disable UFS\n");
+			system_reset();
+		}
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, recheck_ufs_state, NULL);
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c b/src/mainboard/google/brox/variants/baseboard/brox/reset_check.c
similarity index 100%
rename from src/mainboard/google/brox/variants/baseboard/brox/romstage.c
rename to src/mainboard/google/brox/variants/baseboard/brox/reset_check.c