Change in coreboot[master]: haswell: Report only one HPET timer device

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43806 )

Change subject: haswell: Report only one HPET timer device
......................................................................

haswell: Report only one HPET timer device

VT-d checklist fails if there are multiple devices for a single HPET
timer block, and if the bus/dev/fn differs between HPET devices.

Tested on Asrock B85M Pro4, verify VT-d check about HPET is successful.

Change-Id: I68fd074f5440c634ff3ed28c5d423835c81d33b9
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/haswell/acpi.c
M src/southbridge/intel/lynxpoint/lpc.c
2 files changed, 4 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/43806/1

diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index 1df66bc..6a6a124 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -82,10 +82,8 @@
    	current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS,
    					      PCH_IOAPIC_PCI_SLOT, 0);

-		size_t i;
-		for (i = 0; i < 8; ++i)
-			current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS,
-								PCH_HPET_PCI_SLOT, i);
+		current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS,
+							PCH_HPET_PCI_SLOT, 0);
    	acpi_dmar_drhd_fixup(tmp, current);
    }

diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 85fab4d..93b45d0 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -370,10 +370,10 @@
    u32 reg32;
    size_t i;

-	/* Assign unique bus/dev/fn for each HPET */
+	/* Assign the same bus/dev/fn for each HPET */
    for (i = 0; i < 8; ++i)
    	pci_write_config16(dev, LPC_HnBDF(i),
-			PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
+			PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | 0);

/* Move HPET to default address 0xfed00000 and enable it */
    reg32 = RCBA32(HPTC);

[Nico Huber (Code Review)]

Attention is currently required from: Angel Pons.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43806 )

Change subject: haswell: Report only one HPET timer device
......................................................................

Patch Set 4: Code-Review+1

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/43806/comment/a6e7ab21_6a0031cc 
PS3, Line 7: device
s/device/block/?

It looks like the spec doesn't know timers, only blocks. And that
might be the cause of the confusion. If the table only knows blocks,
we can only report one.

Patchset:

PS4: 
Hmmm, merge conflict...

[S] Change in coreboot[master]: haswell: Report only one HPET timer device

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43806?usp=email )

Change subject: haswell: Report only one HPET timer device
......................................................................

Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.