Patch set updated for coreboot: bae2e13 DO NOT MERGE: Intel Common SOC: Add romstage support
Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10050
-gerrit
commit bae2e13eb65a94cb57157d77b44b8fb248fe8710 Author: Lee Leahy leroy.p.leahy@intel.com Date: Mon Apr 20 15:24:54 2015 -0700
DO NOT MERGE: Intel Common SOC: Add romstage support
Provide a common romstage implementation for the Intel SOCs.
BRANCH=none BUG=None TEST=Build for Braswell
Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/soc/intel/common/Kconfig | 38 ++++ src/soc/intel/common/Makefile.inc | 11 +- src/soc/intel/common/fsp_ramstage.c | 154 +++++++++++++++ src/soc/intel/common/gma.h | 176 +++++++++++++++++ src/soc/intel/common/junk.c | 21 +++ src/soc/intel/common/memmap.h | 33 ++++ src/soc/intel/common/mrc_cache.c | 4 +- src/soc/intel/common/raminit.c | 275 +++++++++++++++++++++++++++ src/soc/intel/common/ramstage.h | 36 ++++ src/soc/intel/common/romstage.c | 364 ++++++++++++++++++++++++++++++++++++ src/soc/intel/common/romstage.h | 99 ++++++++++ src/soc/intel/common/spi_loading.c | 152 +++++++++++++++ src/soc/intel/common/stack.c | 173 +++++++++++++++++ src/soc/intel/common/stack.h | 35 ++++ src/soc/intel/common/stage_cache.c | 39 ++++ 15 files changed, 1606 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 8b5cef3..6dd1f57 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -3,6 +3,8 @@ config SOC_INTEL_COMMON help common code for Intel SOCs
+if SOC_INTEL_COMMON + if HAVE_MRC
config CACHE_MRC_SETTINGS @@ -27,6 +29,42 @@ endif # CACHE_MRC_SETTINGS
endif # HAVE_MRC
+config CHIPSET_RESERVED_MEM_BYTES + hex "Size in bytes of chipset reserved memory area" + default 0 + help + If insufficient documentation is available to determine the size of + the chipset reserved memory area by walking the chipset registers, + the CHIPSET_RESERVED_MEM_BYTES may be used as a workaround to account + for the missing pieces of memory. The value specified in bytes is: + + value = TSEG base - top of low usable memory - (any sizes determined + by reading chipset registers) + +config SOC_INTEL_COMMON_FSP_RAM_INIT + bool "FSP: Use the common raminit.c module" + default n + depends on PLATFORM_USES_FSP1_1 + +config SOC_INTEL_COMMON_FSP_ROMSTAGE + bool + default n + config SOC_INTEL_COMMON_RESET bool default n + +config SOC_INTEL_COMMON_STACK + bool + default n + +config SOC_INTEL_COMMON_STAGE_CACHE + bool + default n + +config ROMSTAGE_RAM_STACK_SIZE + hex "Size of the romstage RAM stack in bytes" + default 0x5000 + depends on SOC_INTEL_COMMON_STACK + +endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 6d40aa7..aeae259 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,10 +1,17 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
+romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RAM_INIT) += raminit.c +romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_ROMSTAGE) += romstage.c +romstage-$(CONFIG_SOC_INTEL_COMMON_STACK) += stack.c +romstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c + +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_ramstage.c ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c -romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c -romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c
endif diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c new file mode 100644 index 0000000..2bab2de --- /dev/null +++ b/src/soc/intel/common/fsp_ramstage.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <cbmem.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp_util.h> +#include <romstage_handoff.h> +#include <soc/intel/common/ramstage.h> +#include <stage_cache.h> +#include <timestamp.h> + +/* SOC initialization after FSP silicon init */ +__attribute__((weak)) void soc_after_silicon_init(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +__attribute__((weak)) void soc_save_support_code(void *start, size_t size, + void *entry) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +__attribute__((weak)) void *soc_restore_support_code(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return NULL; +} + +static void fsp_run_silicon_init(void) +{ + FSP_INFO_HEADER *fsp_info_header; + FSP_SILICON_INIT fsp_silicon_init; + EFI_STATUS status; + + /* Find the FSP image */ + fsp_info_header = fsp_get_fih(); + if (fsp_info_header == NULL) { + printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n"); + return; + } + + /* Perform silicon initialization after RAM is configured */ + printk(BIOS_DEBUG, "Calling FspSiliconInit\n"); + fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase + + fsp_info_header->FspSiliconInitEntryOffset); + timestamp_add_now(TS_FSP_SILICON_INIT_START); + status = fsp_silicon_init(NULL); + timestamp_add_now(TS_FSP_SILICON_INIT_END); + printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) + /* Verify the HOBs */ + const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID; + void *hob_list_ptr = get_hob_list(); + int missing_hob = 0; + + if (hob_list_ptr == NULL) + die("ERROR - HOB pointer is NULL!\n"); + print_hob_type_structure(0, hob_list_ptr); + + /* + * Verify that FSP is generating the required HOBs: + * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 + * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit + * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit + * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit + */ + if (NULL == get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) { + printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n"); + missing_hob = 1; + } + if (missing_hob) + die("ERROR - Missing one or more required FSP HOBs!\n"); +#endif + + soc_after_silicon_init(); +} + +static void fsp_cache_save(void) +{ + const struct cbmem_entry *fsp_entry; + FSP_INFO_HEADER *fih; + + fsp_entry = cbmem_entry_find(CBMEM_ID_REFCODE); + + if (fsp_entry == NULL) { + printk(BIOS_ERR, "ERROR: FSP not found in CBMEM.\n"); + return; + } + + fih = fsp_get_fih(); + + if (fih == NULL) { + printk(BIOS_ERR, "ERROR: No FIH found.\n"); + return; + } + + soc_save_support_code(cbmem_entry_start(fsp_entry), + cbmem_entry_size(fsp_entry), fih); +} + +static int fsp_find_and_relocate(void) +{ + struct cbfs_file *file; + void *fih; + + file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "fsp.bin"); + + if (file == NULL) { + printk(BIOS_ERR, "Couldn't find fsp.bin in CBFS.\n"); + return -1; + } + + fih = fsp_relocate(CBFS_SUBHEADER(file), ntohl(file->len)); + + fsp_update_fih(fih); + + return 0; +} + +void intel_silicon_init(void) +{ + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff != NULL && handoff->s3_resume) + fsp_update_fih(soc_restore_support_code()); + else { + fsp_find_and_relocate(); + fsp_cache_save(); + } + + fsp_run_silicon_init(); +} diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h new file mode 100644 index 0000000..9666147 --- /dev/null +++ b/src/soc/intel/common/gma.h @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Chromium OS Authors + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include <types.h> + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + +#endif /* _GMA_H_ */ + diff --git a/src/soc/intel/common/junk.c b/src/soc/intel/common/junk.c new file mode 100644 index 0000000..e90c6e8 --- /dev/null +++ b/src/soc/intel/common/junk.c @@ -0,0 +1,21 @@ +#include <cbmem.h> +#include <reg_script.h> +#include <timestamp.h> + +int cbmem_initialize_id_size(u32 id, u64 size) +{ + return 0; +} + +void cbmem_initialize_empty_id_size(u32 id, u64 size) +{ +} + +void reg_script_run_on_dev(device_t dev, const struct reg_script *step) +{ +} + +void timestamp_early_init(uint64_t base) +{ +} + diff --git a/src/soc/intel/common/memmap.h b/src/soc/intel/common/memmap.h new file mode 100644 index 0000000..840b51e --- /dev/null +++ b/src/soc/intel/common/memmap.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _COMMON_MEMMAP_H_ +#define _COMMON_MEMMAP_H_ + +#include <types.h> + +/* + * mmap_region_granluarity must to return a size which is a positive non-zero + * integer multiple of the SMM size when SMM is in use. When not using SMM, + * this value should be set to 8 MiB. + */ +size_t mmap_region_granluarity(void); +void smm_region(void **start, size_t *size); + +#endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index f854046..018b757 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -149,7 +149,7 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache) return __mrc_cache_get_current(®ion, cache); }
-#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE
/* * romstage code @@ -326,4 +326,4 @@ static void update_mrc_cache(void *unused)
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-#endif /* defined(__PRE_RAM__) */ +#endif /* ENV_ROMSTAGE */ diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c new file mode 100644 index 0000000..4462329 --- /dev/null +++ b/src/soc/intel/common/raminit.c @@ -0,0 +1,275 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <console/console.h> +#include <fsp_util.h> +#include <lib.h> /* hexdump */ +#include <reset.h> +#include <soc/intel/common/memmap.h> +#include <soc/pei_data.h> +#include <soc/romstage.h> +#include <string.h> +#include <timestamp.h> + +void raminit(struct romstage_params *params) +{ + const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID; + EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root; + FSP_INFO_HEADER *fsp_header; + EFI_HOB_RESOURCE_DESCRIPTOR *fsp_memory; + FSP_MEMORY_INIT fsp_memory_init; + FSP_MEMORY_INIT_PARAMS fsp_memory_init_params; + const EFI_GUID fsp_reserved_guid = + FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID; + void *fsp_reserved_memory_area; + FSP_INIT_RT_COMMON_BUFFER fsp_rt_common_buffer; + void *hob_list_ptr; + const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + u32 *mrc_hob; + u32 fsp_reserved_bytes; + EFI_STATUS status; + struct pei_data *pei_ptr; + VPD_DATA_REGION *vpd_ptr; + UPD_DATA_REGION *upd_ptr; + UPD_DATA_REGION upd_data_buffer; + int fsp_verification_failure = 0; +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) + unsigned long int data; + EFI_PEI_HOB_POINTERS hob_ptr; +#endif + + /* + * Find and copy the UPD region to the stack so the platform can modify + * the settings if needed. Modifications to the UPD buffer are done in + * the platform callback code. The platform callback code is also + * responsible for assigning the UpdDataRngPtr to this buffer if any + * updates are made. The default state is to leave the UpdDataRngPtr + * set to NULL. This indicates that the FSP code will use the UPD + * region in the FSP binary. + */ + post_code(0x34); + fsp_header = params->chipset_context; + vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset + + fsp_header->ImageBase); + printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr); + upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset + + fsp_header->ImageBase); + printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr); + memcpy(&upd_data_buffer, upd_ptr, sizeof(upd_data_buffer)); + + /* Zero fill RT Buffer data and start populating fields. */ + memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer)); + pei_ptr = params->pei_data; + if (pei_ptr->boot_mode == SLEEP_STATE_S3) { + fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME; + } else if (pei_ptr->saved_data != NULL) { + fsp_rt_common_buffer.BootMode = + BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + } else { + fsp_rt_common_buffer.BootMode = BOOT_WITH_FULL_CONFIGURATION; + } + fsp_rt_common_buffer.UpdDataRgnPtr = &upd_data_buffer; + fsp_rt_common_buffer.BootLoaderTolumSize = CBMEM_ROOT_SIZE; + + /* Get any board specific changes */ + fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data; + fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer; + fsp_memory_init_params.HobListPtr = &hob_list_ptr; + board_fsp_memory_init_params(params, fsp_header, + &fsp_memory_init_params); + post_code(0x36); + + /* Display the UPD data */ +#if IS_ENABLED(CONFIG_DISPLAY_UPD_DATA) + printk(BIOS_SPEW, "Updated Product Data (UPD):\n"); + hexdump32(BIOS_SPEW, (void *)&upd_data_buffer, sizeof(upd_data_buffer)); +#endif + + /* Call FspMemoryInit to initialize RAM */ + fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase + + fsp_header->FspMemoryInitEntryOffset); + printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init); + printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n", + fsp_memory_init_params.NvsBufferPtr); + printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n", + fsp_memory_init_params.RtBufferPtr); + printk(BIOS_SPEW, " 0x%p: HobListPtr\n", + fsp_memory_init_params.HobListPtr); + + timestamp_add_now(TS_FSP_MEMORY_INIT_START); + status = fsp_memory_init(&fsp_memory_init_params); + post_code(0x37); + timestamp_add_now(TS_FSP_MEMORY_INIT_END); + + printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + if (status != EFI_SUCCESS) + die("ERROR - FspMemoryInit failed to initialize memory!\n"); + + /* Locate the FSP reserved memory area */ + fsp_reserved_bytes = 0; + fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr); + if (fsp_memory == NULL) { + fsp_verification_failure = 1; + printk(BIOS_DEBUG, + "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); + } else { + fsp_reserved_bytes = fsp_memory->ResourceLength; + printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n", + (unsigned long int)fsp_reserved_bytes); + } + + /* Display SMM area */ +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + char *smm_base; + size_t smm_size; + + smm_region((void **)&smm_base, &smm_size); + printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); + printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); +#endif + + /* Migrate CAR data */ + printk(BIOS_DEBUG, "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n", + CONFIG_CHIPSET_RESERVED_MEM_BYTES); + printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); + if (pei_ptr->boot_mode != SLEEP_STATE_S3) { + cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + fsp_reserved_bytes); + } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + fsp_reserved_bytes)) { +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + hard_reset(); +#endif + } + + /* Save the FSP runtime parameters. */ + fsp_set_runtime(params->chipset_context, hob_list_ptr); + + /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ + cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr); + if (cbmem_root == NULL) { + fsp_verification_failure = 1; + printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); + printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n", + fsp_rt_common_buffer.BootLoaderTolumSize); + } + +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) + if (hob_list_ptr == NULL) + die("ERROR - HOB pointer is NULL!\n"); + + /* + * Verify that FSP is generating the required HOBs: + * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 + * 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit + */ + if (NULL != cbmem_root) { + printk(BIOS_DEBUG, + "7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n", + cbmem_root); + data = cbmem_root->PhysicalStart; + printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data); + data = cbmem_root->ResourceLength; + printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data); + } + hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr); + if (NULL == hob_ptr.Raw) { + printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); + fsp_verification_failure = + (params->pei_data->saved_data == NULL) ? 1 : 0; + } else { + printk(BIOS_DEBUG, + "7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n", + hob_ptr.Raw); + } + if (fsp_memory != NULL) { + printk(BIOS_DEBUG, + "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n", + fsp_memory); + data = fsp_memory->PhysicalStart; + printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data); + data = fsp_memory->ResourceLength; + printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data); + } + + /* Verify all the HOBs are present */ + if (fsp_verification_failure) + printk(BIOS_DEBUG, + "ERROR - Missing one or more required FSP HOBs!\n"); + + /* Display the HOBs */ + print_hob_type_structure(0, hob_list_ptr); +#endif + + /* Get the address of the CBMEM region for the FSP reserved memory */ + fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); + printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n", + fsp_reserved_memory_area); + + /* Verify the order of CBMEM root and FSP memory */ + if ((fsp_memory != NULL) && (cbmem_root != NULL) && + (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) { + fsp_verification_failure = 1; + printk(BIOS_DEBUG, + "ERROR - FSP reserved memory above CBMEM root!\n"); + } + + /* Verify that the FSP memory was properly reserved */ + if ((fsp_memory != NULL) && ((fsp_reserved_memory_area == NULL) || + (fsp_memory->PhysicalStart != + (unsigned int)fsp_reserved_memory_area))) { + fsp_verification_failure = 1; + printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n"); +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + if (cbmem_root != NULL) { + size_t delta_bytes = (unsigned int)smm_base + - cbmem_root->PhysicalStart + - cbmem_root->ResourceLength; + printk(BIOS_DEBUG, + "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n", + CONFIG_CHIPSET_RESERVED_MEM_BYTES); + printk(BIOS_DEBUG, + "0x%08x: Chipset reserved bytes reported by FSP\n", + (unsigned int)delta_bytes); + die("Please verify the chipset reserved size\n"); + } +#endif + } + + /* Verify the FSP 1.1 HOB interface */ + if (fsp_verification_failure) + die("ERROR - Coreboot's requirements not met by FSP binary!\n"); + + /* Display the memory configuration */ + report_memory_config(); + + /* Locate the memory configuration data to speed up the next reboot */ + mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); + if (mrc_hob == NULL) + printk(BIOS_DEBUG, + "Memory Configuration Data Hob not present\n"); + else { + pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob); + pei_ptr->data_to_save_size = ALIGN( + ((u32)GET_HOB_LENGTH(mrc_hob)), 16); + } +} diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h new file mode 100644 index 0000000..e46f108 --- /dev/null +++ b/src/soc/intel/common/ramstage.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _INTEL_COMMON_RAMSTAGE_H_ +#define _INTEL_COMMON_RAMSTAGE_H_ + +#include <stdint.h> + +/* Perform Intel silicon init. */ +void intel_silicon_init(void); +/* Called after the silicon init code has run. */ +void soc_after_silicon_init(void); +/* SoC implementation for caching support code. */ +void soc_save_support_code(void *start, size_t size, void *entry); +/* SoC implementation for restoring support code after S3 resume. Returns + * previously passed entry pointer from soc_save_support_code(). */ +void *soc_restore_support_code(void); + +#endif /* _INTEL_COMMON_RAMSTAGE_H_ */ diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c new file mode 100644 index 0000000..bfd0ba1 --- /dev/null +++ b/src/soc/intel/common/romstage.c @@ -0,0 +1,364 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <stdint.h> +#include <arch/cpu.h> +#include <arch/io.h> +#include <arch/cbfs.h> +#include <arch/stages.h> +#include <arch/early_variables.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/x86/mtrr.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <elog.h> +#include <reset.h> +#include <romstage_handoff.h> +#include <soc/intel/common/mrc_cache.h> +#include <soc/pei_wrapper.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <soc/spi.h> +#include <stage_cache.h> +#include <timestamp.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Entry from cache-as-ram.inc. */ +asmlinkage void *romstage_main(unsigned int bist, + uint32_t tsc_low, uint32_t tsc_high, + void *chipset_context) +{ + void *top_of_stack; + struct pei_data pei_data; + struct romstage_params params = { + .bist = bist, + .pei_data = &pei_data, + .chipset_context = chipset_context, + }; + + post_code(0x30); + + /* Save timestamp data */ + timestamp_init((((uint64_t)tsc_high) << 32) | (uint64_t)tsc_low); + timestamp_add_now(TS_START_ROMSTAGE); + + memset(&pei_data, 0, sizeof(pei_data)); + + /* Call into pre-console init code. */ + soc_pre_console_init(¶ms); + mainboard_pre_console_init(¶ms); + + /* Start console drivers */ + console_init(); + + /* Display parameters */ + printk(BIOS_SPEW, "bist: 0x%08x\n", bist); + printk(BIOS_SPEW, "tsc_low: 0x%08x\n", tsc_low); + printk(BIOS_SPEW, "tsc_hi: 0x%08x\n", tsc_high); + printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", + CONFIG_MMCONF_BASE_ADDRESS); + printk(BIOS_INFO, "Using: %s\n", + IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) ? "FSP 1.1" : + (IS_ENABLED(CONFIG_HAVE_MRC) ? "MRC" : + "No Memory Support")); + + /* Display FSP banner */ +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) + printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); + print_fsp_info(params.chipset_context); +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ + + /* Get power state */ + params.power_state = fill_power_state(); + + /* Print useful platform information */ + report_platform_info(); + + /* Set CPU frequency to maximum */ + set_max_freq(); + + /* Perform SOC specific initialization. */ + soc_romstage_init(¶ms); + + /* Call into mainboard. */ + mainboard_romstage_entry(¶ms); + soc_after_ram_init(¶ms); + post_code(0x38); + + top_of_stack = setup_stack_and_mtrrs(); + +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) + printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); + timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ + + return top_of_stack; +} + +/* Entry from the mainboard. */ +void romstage_common(struct romstage_params *params) +{ + const struct mrc_saved_data *cache; + struct romstage_handoff *handoff; + struct pei_data *pei_data; + + post_code(0x32); + + timestamp_add_now(TS_BEFORE_INITRAM); + + pei_data = params->pei_data; + pei_data->boot_mode = params->power_state->prev_sleep_state; + +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) + if (params->power_state->prev_sleep_state != SLEEP_STATE_S3) + boot_count_increment(); +#endif + + /* Perform remaining SOC initialization */ + soc_pre_ram_init(params); + post_code(0x33); + + /* Check recovery and MRC cache */ + params->pei_data->saved_data_size = 0; + params->pei_data->saved_data = NULL; + if (!params->pei_data->disable_saved_data) { + if (recovery_mode_enabled()) { + /* Recovery mode does not use MRC cache */ + printk(BIOS_DEBUG, + "Recovery mode: not using MRC cache.\n"); + } else if (!mrc_cache_get_current(&cache)) { + /* MRC cache found */ + params->pei_data->saved_data_size = cache->size; + params->pei_data->saved_data = &cache->data[0]; + } else if (params->pei_data->boot_mode == SLEEP_STATE_S3) { + /* Waking from S3 and no cache. */ + printk(BIOS_DEBUG, + "No MRC cache found in S3 resume path.\n"); + post_code(POST_RESUME_FAILURE); + hard_reset(); + } else { + printk(BIOS_DEBUG, "No MRC cache found.\n"); + mainboard_check_ec_image(params); + } + } + + /* Initialize RAM */ + raminit(params); + timestamp_add_now(TS_AFTER_INITRAM); + + /* Save MRC output */ + printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, + pei_data->data_to_save_size); + if (params->pei_data->boot_mode != SLEEP_STATE_S3) { + if (params->pei_data->data_to_save_size != 0 && + params->pei_data->data_to_save != NULL) { + mrc_cache_stash_data(params->pei_data->data_to_save, + params->pei_data->data_to_save_size); + } + } + + /* Save DIMM information */ + mainboard_save_dimm_info(params); + + /* Create romstage handof information */ + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (params->power_state->prev_sleep_state == + SLEEP_STATE_S3); + else { + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + hard_reset(); + } + +#if IS_ENABLED(CONFIG_CHROMEOS) + /* Normalize the sleep state to what init_chromeos() wants for S3: 2 */ + init_chromeos((params->power_state->prev_sleep_state == SLEEP_STATE_S3) + ? 2 : 0); +#endif +} + +asmlinkage void romstage_after_car(void *chipset_context) +{ + if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { + timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END); + printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n"); + soc_after_temp_ram_exit(); + } + + timestamp_add_now(TS_END_ROMSTAGE); + + /* Run vboot verification if configured. */ + vboot_verify_firmware(romstage_handoff_find_or_add()); + + /* Load the ramstage. */ + copy_and_run(); + die("ERROR - Failed to load ramstage!"); +} + +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +__attribute__((weak)) void board_fsp_memory_init_params( + struct romstage_params *params, + FSP_INFO_HEADER *fsp_header, + FSP_MEMORY_INIT_PARAMS * fsp_memory_init_params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ + +/* Initialize the power state */ +__attribute__((weak)) struct chipset_power_state *fill_power_state(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return NULL; +} + +__attribute__((weak)) void mainboard_check_ec_image( + struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + struct pei_data *pei_data; + + pei_data = params->pei_data; + if (params->pei_data->boot_mode == SLEEP_STATE_S0) { + /* Ensure EC is running RO firmware. */ + google_chromeec_check_ec_image(EC_IMAGE_RO); + } +#endif +} + +/* Board initialization before the console is enabled */ +__attribute__((weak)) void mainboard_pre_console_init( + struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Board initialization before and after RAM is enabled */ +__attribute__((weak)) void mainboard_romstage_entry( + struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + + post_code(0x31); + + /* Initliaze memory */ + romstage_common(params); +} + +/* Used by MRC images to save DIMM information */ +__attribute__((weak)) void mainboard_save_dimm_info( + struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Get the memory configuration data */ +__attribute__((weak)) int mrc_cache_get_current( + const struct mrc_saved_data **cache) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return -1; +} + +/* Save the memory configuration data */ +__attribute__((weak)) int mrc_cache_stash_data(void *data, size_t size) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return -1; +} + +/* Transition RAM from off or self-refresh to active */ +__attribute__((weak)) void raminit(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + post_code(0x34); + die("ERROR - No RAM initialization specified!\n"); +} + +void ramstage_cache_invalid(void) +{ +#if IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) + /* Perform cold reset on invalid ramstage cache. */ + hard_reset(); +#endif +} + +/* Display the memory configuration */ +__attribute__((weak)) void report_memory_config(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Display the platform configuration */ +__attribute__((weak)) void report_platform_info(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Choose top of stack and setup MTRRs */ +__attribute__((weak)) void *setup_stack_and_mtrrs(void) +{ + printk(BIOS_ERR, "WEAK: %s/%s called\n", __FILE__, __func__); + die("ERROR - Must specify top of stack!\n"); + return NULL; +} + +/* Speed up the CPU to the maximum frequency */ +__attribute__((weak)) void set_max_freq(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization after RAM is enabled */ +__attribute__((weak)) void soc_after_ram_init(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization after temporary RAM is disabled */ +__attribute__((weak)) void soc_after_temp_ram_exit(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization before the console is enabled */ +__attribute__((weak)) void soc_pre_console_init(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization before RAM is enabled */ +__attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization after console is enabled */ +__attribute__((weak)) void soc_romstage_init(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Ensure the EC is in the right mode for recovery */ + google_chromeec_early_init(); +#endif +} diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h new file mode 100644 index 0000000..2747665 --- /dev/null +++ b/src/soc/intel/common/romstage.h @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _COMMON_ROMSTAGE_H_ +#define _COMMON_ROMSTAGE_H_ + +#include <stdint.h> +#include <arch/cpu.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#include <fsp_util.h> +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ +#include <soc/pei_data.h> +#include <soc/pm.h> /* chip_power_state */ + +struct romstage_params { + unsigned long bist; + struct chipset_power_state *power_state; + struct pei_data *pei_data; + void *chipset_context; +}; + +/* + * FSP Boot Flow: + * 1. src/cpu/x86/16bit/reset.inc + * 2. src/cpu/x86/16bit/entry.inc + * 3. other modules + * 4. src/drivers/intel/fsp/fsp_1_1.inc + * 5. src/drivers/intel/fsp/fsp_util.c/find_fsp + * 6. FSP binary/TempRamInit + * 7. src/drivers/intel/fsp/fsp_1_1.inc - return + * 8. src/soc/intel/common/romstage.c/romstage_main + * 9 src/soc/.../romstage/.../soc_pre_console_init + * 10 src/console/console.c/console_init + * 11 src/soc/.../romstage/.../soc_romstage_init + * 12. src/mainboard/.../romstage.c/mainboard_romstage_entry + * 13. src/soc/intel/skylake/romstage/romstage.c/romstage_common + * 14 src/soc/.../romstage/.../soc_pre_raminit + * 15. FSP binary/MemoryInit + * 16. src/soc/intel/common/romstage.c/romstage_common - return + * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return + * 18. src/soc/intel/common/romstage.c/romstage_main - return + * 19. src/soc/intel/skylake/stack.c/setup_stack_and_mttrs + * 20. src/drivers/intel/fsp/fsp_1_1.inc - return, cleanup + * after call to romstage_main + * 21. FSP binary/TempRamExit + * 22. src/soc/intel/common/romstage.c/romstage_after_car + * 23. FSP binary/SiliconInit + * 24. src/soc/intel/common/romstage.c/romstage_after_car - return + * 25. src/soc/intel/.../chip.c/skylake_final + * 26. src/drivers/intel/fsp/fsp_util.c/fsp_notify + * 27. FSP binary/FspNotify + * 28. src/soc/intel/.../ramstage.c/fsp_final + * 29. src/drivers/intel/fsp/fsp_util.c/fsp_notify + * 30. FSP binary/FspNotify + */ + +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +void board_fsp_memory_init_params( + struct romstage_params *params, + FSP_INFO_HEADER *fsp_header, + FSP_MEMORY_INIT_PARAMS * fsp_memory_init_params); +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ +void mainboard_check_ec_image(struct romstage_params *params); +void mainboard_pre_console_init(struct romstage_params *params); +void mainboard_romstage_entry(struct romstage_params *params); +void mainboard_save_dimm_info(struct romstage_params *params); +void raminit(struct romstage_params *params); +void report_memory_config(void); +void report_platform_info(void); +asmlinkage void romstage_after_car(void *chipset_context); +void romstage_common(struct romstage_params *params); +asmlinkage void *romstage_main(unsigned int bist, uint32_t tsc_lo, + uint32_t tsc_high, void *chipset_context); +void *setup_stack_and_mtrrs(void); +void set_max_freq(void); +void soc_after_ram_init(struct romstage_params *params); +void soc_after_temp_ram_exit(void); +void soc_pre_console_init(struct romstage_params *params); +void soc_pre_ram_init(struct romstage_params *params); +void soc_romstage_init(struct romstage_params *params); + +#endif /* _COMMON_ROMSTAGE_H_ */ diff --git a/src/soc/intel/common/spi_loading.c b/src/soc/intel/common/spi_loading.c new file mode 100644 index 0000000..fe3522b --- /dev/null +++ b/src/soc/intel/common/spi_loading.c @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/byteorder.h> +#include <boot/coreboot_tables.h> +#include <cbmem.h> +#include <cbfs.h> +#include <console/console.h> +#include <stdlib.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#define CACHELINE_SIZE 64 +#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) +#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) + +static void *find_mirror_buffer(int len) +{ + int nentries; + int i; + struct lb_memory *mem; + void *buffer; + + len = ALIGN(len, 4096); + + mem = get_lb_mem(); + nentries = (mem->size - sizeof(*mem)) / sizeof(mem->map[0]); + + /* + * Find the highest RAM entry that accommodates the lenth provide + * while falling below 4GiB. + */ + buffer = NULL; + for (i = 0; i < nentries; i++) { + const uint64_t max_addr = 1ULL << 32; + uint64_t start; + uint64_t size; + struct lb_memory_range *r; + + r = &mem->map[i]; + + if (r->type != LB_MEM_RAM) + continue; + + start = unpack_lb64(r->start); + if (start >= max_addr) + continue; + + size = unpack_lb64(r->size); + if (size < len) + continue; + + /* Adjust size of buffer if range exceeds max address. */ + if (start + size > max_addr) + size = max_addr - start; + + if (size < len) + continue; + + buffer = (void *)(uintptr_t)(start + size - len); + } + + return buffer; +} + +/* + * Mirror the payload file to the default SMM location if it is small enough. + * The default SMM region can be used since no one is using the memory at this + * location at this stage in the boot. + */ +static void *spi_mirror(void *file_start, int file_len) +{ + int alignment_diff; + char *src; + char *dest; + + alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); + + /* + * Adjust file length so that the start and end points are aligned to a + * cacheline. Coupled with the ROM caching in the CPU the SPI hardware + * will read and cache full length cachelines. It will also prefetch + * data as well. Once things are mirrored in memory all accesses should + * hit the CPUs cache. + */ + file_len += alignment_diff; + file_len = ALIGN(file_len, CACHELINE_SIZE); + + printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); + + dest = find_mirror_buffer(file_len); + + /* + * Just pass back the pointer to ROM space if a buffer could not + * be found to mirror into. + */ + if (dest == NULL) + return file_start; + + src = (void *)(CACHELINE_MASK & (long)file_start); + /* + * Note that if mempcy is not using 32-bit moves the performance will + * degrade because the SPI hardware prefetchers look for + * cacheline-aligned 32-bit accesses to kick in. + */ + memcpy(dest, src, file_len); + + /* Provide pointer into mirrored space. */ + return &dest[alignment_diff]; +} + +void *cbfs_load_payload(struct cbfs_media *media, const char *name) +{ + int file_len; + void *file_start; + struct cbfs_file *file; + + file_start = vboot_get_payload(&file_len); + + if (file_start != NULL) + return spi_mirror(file_start, file_len); + + file = cbfs_get_file(media, name); + + if (file == NULL) + return NULL; + + if (ntohl(file->type) != CBFS_TYPE_PAYLOAD) + return NULL; + + file_len = ntohl(file->len); + + file_start = CBFS_SUBHEADER(file); + + return spi_mirror(file_start, file_len); +} diff --git a/src/soc/intel/common/stack.c b/src/soc/intel/common/stack.c new file mode 100644 index 0000000..3e6e4b7 --- /dev/null +++ b/src/soc/intel/common/stack.c @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include "memmap.h" +#include "romstage.h" +#include "stack.h" +#include <stdlib.h> + +const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE; + +/* + * Romstage needs quite a bit of stack for decompressing images since the lzma + * lib keeps its state on the stack during romstage. + */ +static unsigned long choose_top_of_stack(void) +{ + unsigned long stack_top; + + /* cbmem_add() does a find() before add(). */ + stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, + romstage_ram_stack_size); + stack_top += romstage_ram_stack_size; + return stack_top; +} + +/* + * setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. + */ +void *setup_stack_and_mtrrs(void) +{ + size_t alignment; + uint32_t aligned_ram; + uint32_t mtrr_mask_upper; + int num_mtrrs; + uint32_t *slot; + unsigned long top_of_stack; + + /* Top of stack needs to be aligned to a 8-byte boundary. */ + top_of_stack = choose_top_of_stack(); + slot = (void *)top_of_stack; + num_mtrrs = 0; + + /* + * The upper bits of the MTRR mask need to set according to the number + * of physical address bits. + */ + mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; + + /* + * The order for each MTRR is value then base with upper 32-bits of + * each value coming before the lower 32-bits. The reasoning for + * this ordering is to create a stack layout like the following: + * +0: Number of MTRRs + * +4: MTRR base 0 31:0 + * +8: MTRR base 0 63:32 + * +12: MTRR mask 0 31:0 + * +16: MTRR mask 0 63:32 + * +20: MTRR base 1 31:0 + * +24: MTRR base 1 63:32 + * +28: MTRR mask 1 31:0 + * +32: MTRR mask 1 63:32 + */ + + /* Cache the ROM as WP just below 4GiB. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); + num_mtrrs++; + + /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK); + num_mtrrs++; + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | + * | | + * +-------------------------+ Chipset reserved mem base (aligned) + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ top_of_ram (not aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + * + * Requirement: + * Chipset reserved memory base needs to be aligned to a multiple + * of TSEG size when SMM is in use or 8 Mib when SMM is not supported + * by the SOC/board configuration. + */ + + /* + * Cache the stack and the other CBMEM entries as well as part or all + * of the FSP reserved memory region. + */ + alignment = mmap_region_granluarity(); + aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size, + alignment); + + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK); + num_mtrrs++; + +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + void *smm_base; + size_t smm_size; + uint32_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is not + * restricted to SMM mode until SMM has been relocated. By setting + * the region to cacheable it provides faster access when relocating + * the SMM handler as well as using the TSEG region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uint32_t)smm_base; + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); + num_mtrrs++; +#endif + + /* + * Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + slot = stack_push32(slot, num_mtrrs); + return slot; +} + diff --git a/src/soc/intel/common/stack.h b/src/soc/intel/common/stack.h new file mode 100644 index 0000000..850a070 --- /dev/null +++ b/src/soc/intel/common/stack.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _COMMON_STACK_H_ +#define _COMMON_STACK_H_ + +#include <stdint.h> + +static inline void *stack_push32(void *stack, uint32_t value) +{ + uint32_t *stack32 = stack; + + stack32 = &stack32[-1]; + *stack32 = value; + return stack32; +} + +#endif /* _COMMON_STACK_H_ */ diff --git a/src/soc/intel/common/stage_cache.c b/src/soc/intel/common/stage_cache.c new file mode 100644 index 0000000..2dd4e47 --- /dev/null +++ b/src/soc/intel/common/stage_cache.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <soc/intel/common/memmap.h> +#include <soc/smm.h> +#include <stage_cache.h> + +void stage_cache_external_region(void **base, size_t *size) +{ + char *smm_base; + size_t smm_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + /* + * The ramstage cache lives in the TSEG region. + * The top of ram is defined to be the TSEG base address. + */ + smm_region((void **)&smm_base, &smm_size); + *size = cache_size; + *base = (void *)(&smm_base[smm_size - cache_size]); +}
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Leroy P Leahy