Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S storage related configs

[Werner Zeh (Code Review)]

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55082 )

Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs
......................................................................

soc/intel/elkhartlake: Update FSP-S storage related configs

Further add initial Silicon UPD storage settings:
- SATA
- SD card
- eMMC

Signed-off-by: Lean Sheng Tan 
Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55082
Tested-by: build bot (Jenkins) 
Reviewed-by: Werner Zeh 
Reviewed-by: Mario Scheithauer 
---
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/fsp_params.c
4 files changed, 80 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Werner Zeh: Looks good to me, approved
  Mario Scheithauer: Looks good to me, approved

diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
index be2b6c9..d6dca67 100644
--- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
@@ -70,6 +70,18 @@
    register "PcieClkSrcClkReq[4]" = "0x4"
    register "PcieClkSrcClkReq[5]" = "0x5"

+	# Storage (SATA/SDCARD/EMMC) related UPDs
+	register "SataSalpSupport" = "1"
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "1"
+
+	register "ScsEmmcHs400Enabled" = "1"
+	register "ScsEmmcDdr50Enabled" = "1"
+	register "SdCardPowerEnableActiveHigh" = "1"
+
+	# LPSS Serial IO (I2C/UART/GSPI) related UPDs
    register "SerialIoI2cMode" = "{
    	[PchSerialIoIndexI2C0] = PchSerialIoPci,
    	[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index b55884c..a522db5 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -109,6 +109,10 @@
    int
    default 7

+config MAX_SATA_PORTS
+	int
+	default 2
+
 config MAX_PCIE_CLOCK_SRC
    int
    default 6
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index ebe14d5..f51e723 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -90,8 +90,22 @@
    /* SATA related */
    uint8_t SataMode;
    uint8_t SataSalpSupport;
-	uint8_t SataPortsEnable[8];
-	uint8_t SataPortsDevSlp[8];
+	uint8_t SataPortsEnable[CONFIG_MAX_SATA_PORTS];
+	uint8_t SataPortsDevSlp[CONFIG_MAX_SATA_PORTS];
+	/*
+	 * Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
+	 * Default 0. Setting this to 1 disables the SATA Power Optimizer.
+	 */
+	uint8_t SataPwrOptimizeDisable;
+	/*
+	 * SATA Port Enable Dito Config.
+	 * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
+	 */
+	uint8_t SataPortsEnableDitoConfig[CONFIG_MAX_SATA_PORTS];
+	/* SataPortsDmVal is the DITO multiplier. Default is 15. */
+	uint8_t SataPortsDmVal[CONFIG_MAX_SATA_PORTS];
+	/* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
+	uint16_t SataPortsDitoVal[CONFIG_MAX_SATA_PORTS];

/* Audio related */
    uint8_t PchHdaDspEnable;
@@ -135,6 +149,7 @@

/* eMMC and SD */
    uint8_t ScsEmmcHs400Enabled;
+	uint8_t ScsEmmcDdr50Enabled;

/* Enable if SD Card Power Enable Signal is Active High */
    uint8_t SdCardPowerEnableActiveHigh;
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index 98c939f..f02d20e 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -15,6 +15,13 @@
 #include <soc/soc_chip.h>
 #include <string.h>

+/* SATA DEVSLP idle timeout default values */
+#define DEF_DMVAL		15
+#define DEF_DITOVAL_MS		625
+
+/* Native function controls pads termination */
+#define GPIO_TERM_NATIVE	0x1F
+
 /*
  * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
  * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
@@ -231,6 +238,46 @@
    	params->PcieRpVc1TcMap[i] = 0x60;
    }

+	/* SATA config */
+	dev = pcidev_path_on_root(PCH_DEVFN_SATA);
+	params->SataEnable = is_dev_enabled(dev);
+	if (params->SataEnable) {
+		params->SataMode = config->SataMode;
+		params->SataSalpSupport = config->SataSalpSupport;
+		params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
+
+		for (i = 0; i < CONFIG_MAX_SATA_PORTS; i++) {
+			params->SataPortsEnable[i] = config->SataPortsEnable[i];
+			params->SataPortsDevSlp[i] = config->SataPortsDevSlp[i];
+			if (config->SataPortsEnableDitoConfig[i]) {
+				params->SataPortsDmVal[i] =
+					config->SataPortsDmVal[i] ? : DEF_DMVAL;
+				params->SataPortsDitoVal[i] =
+					config->SataPortsDitoVal[i] ? : DEF_DITOVAL_MS;
+			}
+		}
+	}
+
+	/* SDCard config */
+	dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
+	params->ScsSdCardEnabled = is_dev_enabled(dev);
+	if (params->ScsSdCardEnabled) {
+		params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;
+		params->SdCardGpioCmdPadTermination = GPIO_TERM_NATIVE;
+		params->SdCardGpioDataPadTermination[0] = GPIO_TERM_NATIVE;
+		params->SdCardGpioDataPadTermination[1] = GPIO_TERM_NATIVE;
+		params->SdCardGpioDataPadTermination[2] = GPIO_TERM_NATIVE;
+		params->SdCardGpioDataPadTermination[3] = GPIO_TERM_NATIVE;
+	}
+
+	/* eMMC config */
+	dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
+	params->ScsEmmcEnabled = is_dev_enabled(dev);
+	if (params->ScsEmmcEnabled) {
+		params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
+		params->ScsEmmcDdr50Enabled = config->ScsEmmcDdr50Enabled;
+	}
+
    /* Override/Fill FSP Silicon Param for mainboard */
    mainboard_silicon_init_params(params);
 }