[M] Change in coreboot[master]: soc/amd/mendocino: Remove the SPL DPTC parameter

[Chris Wang (Code Review)]

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Isaac Lee, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held.

Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73124 )

Change subject: soc/amd/mendocino: Remove the SPL DPTC parameter
......................................................................

Patch Set 6:

(1 comment)

File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/73124/comment/7dd00919_cf4796a9 
PS6, Line 263: # Remove the sustained_power_limit_mW when STT is enabled
             : 	register "sustained_power_limit_mW"              = "15000"
> Should the sustained_power_limit_mW move to skyrim/overridetree.cb from here? […]

It may need to submit another CL if we want to move 'sustained_power_limit_mW' from the baseboard to each variant. This is because there are still other variants that follow the baseboard and STT has not been enabled yet. If we move 'sustained_power_limit_mW' to 'skyrim/overridetree', it would mean that we need to apply the same value to each variant, which would be duplicated."