Attention is currently required from: Alexander Couzens, Angel Pons, Martin L Roth, Patrick Rudolph.
Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76962?usp=email )
Change subject: SNB+MRC boards: Do not redo PEI data struct in hook ......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/roda/rv11/variants/rw11/early_init.c:
https://review.coreboot.org/c/coreboot/+/76962/comment/591b02b0_697af504 : PS5, Line 64: pcie_init
set by northbridge_fill_pei_data?
From what I understand reading northbridge_fill_pei_data(), it sets this value to 1 if the system has Ivy Bridge CPU and PCI device 1:0 aka peg10 is enabled in devicetree. Vendor info on this system indicates it has a IVB i7 but peg10 isn't enabled, thus it would become 0. Since I have no hardware to verify, I lean towards maintaining status quo.
https://review.coreboot.org/c/coreboot/+/76962/comment/a3e7a5d1_5fb219e1 : PS5, Line 65: usb3
Use devicetree setting register "usb3.mode"= ... […]
Fully migrate this and USB config to devicetree? (This also needs to be addressed but that setting can assume the native init data format instead, like being done for SPD addresses by later patches in this train.)
(I'll go ahead and migrate these settings to devicetree, if they aren't controlled by nvram options.)
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Keith Hui (Code Review)