HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37828 )
Change subject: src: Replace min/max() with MIN/MAX() ......................................................................
src: Replace min/max() with MIN/MAX()
Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/lib/edid.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/nehalem/raminit.c M src/soc/mediatek/common/cbmem.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/rockchip/common/cbmem.c M src/soc/sifive/fu540/cbmem.c 7 files changed, 33 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37828/1
diff --git a/src/lib/edid.c b/src/lib/edid.c index fd7f5ba..4a2f07a 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -29,12 +29,12 @@ */
#include <assert.h> +#include <commonlib/helpers.h> #include <stddef.h> #include <console/console.h> #include <ctype.h> #include <stdint.h> #include <string.h> -#include <stdlib.h> #include <edid.h> #include <vbe.h>
@@ -178,7 +178,7 @@
memset(ret, 0, sizeof(ret));
- for (i = 0; i < min(len, EDID_ASCII_STRING_LENGTH); i++) { + for (i = 0; i < MIN(len, EDID_ASCII_STRING_LENGTH); i++) { if (seen_newline) { if (x[i] != 0x20) { *valid_termination = 0; @@ -1691,7 +1691,7 @@ { /* Caller should pass a supported value, everything else is BUG(). */ assert(fb_bpp == 32 || fb_bpp == 24 || fb_bpp == 16); - row_byte_alignment = max(row_byte_alignment, 1); + row_byte_alignment = MAX(row_byte_alignment, 1);
edid->framebuffer_bits_per_pixel = fb_bpp; edid->bytes_per_line = ALIGN_UP(edid->mode.ha * diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index a2c7643..b1da177 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */
+#include <commonlib/helpers.h> #include <stdint.h> -#include <stdlib.h> #include <arch/cpu.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -436,7 +436,7 @@
unsigned int clock = 8000 / tCKmin; if ((clock > sysinfo->max_ddr3_mt / 2) || (clock > fsb_mhz / 2)) { - int new_clock = min(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2); + int new_clock = MIN(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2); printk(BIOS_SPEW, "DIMMs support %d MHz, but chipset only runs at up to %d. Limiting...\n", clock, new_clock); clock = new_clock; diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index a393cb7..a074fac 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */
-#include <stdlib.h> #include <console/console.h> +#include <commonlib/helpers.h> #include <string.h> #include <arch/io.h> #include <device/mmio.h> @@ -571,7 +571,7 @@ spd[channel][slot][CAS_LATENCIES_MSB] << 8));
- max_clock_index = min(3, info->max_supported_clock_speed_index); + max_clock_index = MIN(3, info->max_supported_clock_speed_index);
cycletime = min_cycletime[max_clock_index]; cas_latency_time = min_cas_latency_time[max_clock_index]; @@ -586,11 +586,11 @@ spd[channel][slot][TIMEBASE_DIVIDEND] / info->spd[channel][slot][TIMEBASE_DIVISOR]; cycletime = - max(cycletime, + MAX(cycletime, timebase * info->spd[channel][slot][CYCLETIME]); cas_latency_time = - max(cas_latency_time, + MAX(cas_latency_time, timebase * info-> spd[channel][slot][CAS_LATENCY_TIME]); @@ -865,7 +865,7 @@ if (info->revision_flag_1) some_delay_2_ps = halfcycle_ps(info) >> 6; some_delay_2_ps += - max(some_delay_1_ps - 30, + MAX(some_delay_1_ps - 30, 2 * halfcycle_ps(info) * (some_delay_1_cycle_ceil - 1) + 1000) + 375; some_delay_3_ps = @@ -977,8 +977,8 @@ clock_speed_index]; } } - min_of_unk_2 = min(min_of_unk_2, a); - min_of_unk_2 = min(min_of_unk_2, b); + min_of_unk_2 = MIN(min_of_unk_2, a); + min_of_unk_2 = MIN(min_of_unk_2, b); if (rank == 0) { sum += a; count++; @@ -993,7 +993,7 @@ clock_speed_index]; if (unk1 >= t) max_of_unk = - max(max_of_unk, + MAX(max_of_unk, unk1 - t); } } @@ -1005,7 +1005,7 @@ [channel]] [info->clock_speed_index] + min_of_unk_2; if (unk1 >= t) - max_of_unk = max(max_of_unk, unk1 - t); + max_of_unk = MAX(max_of_unk, unk1 - t); } }
@@ -1177,7 +1177,7 @@ info->total_memory_mb = total_mb[0] + total_mb[1];
info->interleaved_part_mb = - pre_jedec ? 0 : 2 * min(total_mb[0], total_mb[1]); + pre_jedec ? 0 : 2 * MIN(total_mb[0], total_mb[1]); info->non_interleaved_part_mb = total_mb[0] + total_mb[1] - info->interleaved_part_mb; channel_0_non_interleaved = total_mb[0] - info->interleaved_part_mb / 2; @@ -1247,7 +1247,7 @@ halfcycle_ps(info) + 2230); some_delay_3_half_cycles = - min((some_delay_2_half_cycles + + MIN((some_delay_2_half_cycles + (frequency_11(info) * 2) * (28 - some_delay_2_half_cycles) / (frequency_11(info) * 2 - @@ -1351,7 +1351,7 @@
program_modules_memory_map(info, 1);
- MCHBAR16(0x610) = (min(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) + MCHBAR16(0x610) = (MIN(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) | (MCHBAR16(0x610) & 0x1C3) | 0x3C; MCHBAR16_OR(0x612, 0x100); MCHBAR16_OR(0x214, 0x3E00); @@ -1421,12 +1421,12 @@ if (TOM == 4096) TOM = 4032; TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64); - TOLUD = ALIGN_DOWN(min(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) + TOLUD = ALIGN_DOWN(MIN(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) , TOUUD), 64); memory_remap = 0; if (TOUUD - TOLUD > 64) { memory_remap = 1; - REMAPbase = max(4096, TOUUD); + REMAPbase = MAX(4096, TOUUD); TOUUD = TOUUD - TOLUD + 4096; } if (TOUUD > 4096) @@ -1472,7 +1472,7 @@ memory_map[0] = ALIGN_DOWN(uma_base_gtt, 64) | 1; memory_map[1] = 4096; for (i = 0; i < ARRAY_SIZE(memory_map); i++) { - current_limit = max(current_limit, memory_map[i] & ~1); + current_limit = MAX(current_limit, memory_map[i] & ~1); pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80, (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2); @@ -2737,9 +2737,9 @@ upper_margin = timings[center_178][channel][slot][rank][lane].largest - result; if (upper_margin < 10 && lower_margin > 10) - result -= min(lower_margin - 10, 10 - upper_margin); + result -= MIN(lower_margin - 10, 10 - upper_margin); if (upper_margin > 10 && lower_margin < 10) - result += min(upper_margin - 10, 10 - lower_margin); + result += MIN(upper_margin - 10, 10 - lower_margin); return result; }
@@ -3258,8 +3258,8 @@ g = gcd(freq1, freq2); freq1_reduced = freq1 / g; freq2_reduced = freq2 / g; - freq_min_reduced = min(freq1_reduced, freq2_reduced); - freq_max_reduced = max(freq1_reduced, freq2_reduced); + freq_min_reduced = MIN(freq1_reduced, freq2_reduced); + freq_max_reduced = MAX(freq1_reduced, freq2_reduced);
common_time_unit_ps = div_roundup(900000, lcm(freq1, freq2)); freq3 = div_roundup(num_cycles_2, common_time_unit_ps) - 1; @@ -3527,7 +3527,7 @@ for (rank = 0; rank < NUM_RANKS; rank++) if (info->populated_ranks[channel][slot][rank]) for (lane = 0; lane < 8 + info->use_ecc; lane++) - ret = max(ret, read_500(info, channel, + ret = MAX(ret, read_500(info, channel, get_timing_register_addr (lane, 0, slot, rank), 9)); diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 1a55d01..accafeb 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -14,8 +14,8 @@ */
#include <cbmem.h> +#include <commonlib/helpers.h> #include <stddef.h> -#include <stdlib.h> #include <symbols.h> #include <soc/emi.h>
@@ -23,5 +23,5 @@
void *cbmem_top_chipset(void) { - return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index a22d7e2..492238a 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -308,7 +308,7 @@ int matches = 0, sum = 0;
/* fine tune range from 0 to 127 */ - fine_val = min(max(fine_val, 0 - delta[0]), 127 - delta[6]); + fine_val = MIN(MAX(fine_val, 0 - delta[0]), 127 - delta[6]);
/* test gw fine tune */ for (i = 0; i < ARRAY_SIZE(delta); i++) { @@ -443,7 +443,7 @@
if (is_dual_rank(channel, sdram_params)) { /* RANKINCTL_ROOT1 = DQSINCTL + reg_TX_DLY_DQSGATE */ - value = min(opt_gw_coarse_value[channel][0], + value = MIN(opt_gw_coarse_value[channel][0], opt_gw_coarse_value[channel][1]) >> 2;
clrsetbits32(&ch[channel].ao_regs->dummy, 0xf, value); diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 6e3aabb..ccaa624 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -14,13 +14,13 @@ */
#include <cbmem.h> +#include <commonlib/helpers.h> #include <soc/addressmap.h> #include <soc/sdram.h> -#include <stdlib.h> #include <symbols.h>
void *cbmem_top_chipset(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index a7de16c..b6b568d 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -14,13 +14,13 @@ */
#include <cbmem.h> +#include <commonlib/helpers.h> #include <soc/addressmap.h> #include <soc/sdram.h> -#include <stdlib.h> #include <symbols.h>
void *cbmem_top_chipset(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); }
Hello Patrick Rudolph, ron minnich, Julius Werner, build bot (Jenkins), Philipp Hug,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37828
to look at the new patch set (#2).
Change subject: src: Replace min/max() with MIN/MAX() ......................................................................
src: Replace min/max() with MIN/MAX()
Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/lib/edid.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/nehalem/raminit.c M src/soc/mediatek/common/cbmem.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/rockchip/common/cbmem.c M src/soc/sifive/fu540/cbmem.c 7 files changed, 34 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37828/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37828 )
Change subject: src: Replace min/max() with MIN/MAX() ......................................................................
Patch Set 2: Code-Review+1
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37828 )
Change subject: src: Replace min/max() with MIN/MAX() ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37828 )
Change subject: src: Replace min/max() with MIN/MAX() ......................................................................
src: Replace min/max() with MIN/MAX()
Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/37828 Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Patrick Georgi pgeorgi@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/lib/edid.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/nehalem/raminit.c M src/soc/mediatek/common/cbmem.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/rockchip/common/cbmem.c M src/soc/sifive/fu540/cbmem.c 7 files changed, 34 insertions(+), 34 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Kyösti Mälkki: Looks good to me, but someone else must approve
diff --git a/src/lib/edid.c b/src/lib/edid.c index fd7f5ba..4a2f07a 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -29,12 +29,12 @@ */
#include <assert.h> +#include <commonlib/helpers.h> #include <stddef.h> #include <console/console.h> #include <ctype.h> #include <stdint.h> #include <string.h> -#include <stdlib.h> #include <edid.h> #include <vbe.h>
@@ -178,7 +178,7 @@
memset(ret, 0, sizeof(ret));
- for (i = 0; i < min(len, EDID_ASCII_STRING_LENGTH); i++) { + for (i = 0; i < MIN(len, EDID_ASCII_STRING_LENGTH); i++) { if (seen_newline) { if (x[i] != 0x20) { *valid_termination = 0; @@ -1691,7 +1691,7 @@ { /* Caller should pass a supported value, everything else is BUG(). */ assert(fb_bpp == 32 || fb_bpp == 24 || fb_bpp == 16); - row_byte_alignment = max(row_byte_alignment, 1); + row_byte_alignment = MAX(row_byte_alignment, 1);
edid->framebuffer_bits_per_pixel = fb_bpp; edid->bytes_per_line = ALIGN_UP(edid->mode.ha * diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index a2c7643..b1da177 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */
+#include <commonlib/helpers.h> #include <stdint.h> -#include <stdlib.h> #include <arch/cpu.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -436,7 +436,7 @@
unsigned int clock = 8000 / tCKmin; if ((clock > sysinfo->max_ddr3_mt / 2) || (clock > fsb_mhz / 2)) { - int new_clock = min(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2); + int new_clock = MIN(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2); printk(BIOS_SPEW, "DIMMs support %d MHz, but chipset only runs at up to %d. Limiting...\n", clock, new_clock); clock = new_clock; diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index a393cb7..8a2837e 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */
-#include <stdlib.h> #include <console/console.h> +#include <commonlib/helpers.h> #include <string.h> #include <arch/io.h> #include <device/mmio.h> @@ -571,7 +571,7 @@ spd[channel][slot][CAS_LATENCIES_MSB] << 8));
- max_clock_index = min(3, info->max_supported_clock_speed_index); + max_clock_index = MIN(3, info->max_supported_clock_speed_index);
cycletime = min_cycletime[max_clock_index]; cas_latency_time = min_cas_latency_time[max_clock_index]; @@ -586,11 +586,11 @@ spd[channel][slot][TIMEBASE_DIVIDEND] / info->spd[channel][slot][TIMEBASE_DIVISOR]; cycletime = - max(cycletime, + MAX(cycletime, timebase * info->spd[channel][slot][CYCLETIME]); cas_latency_time = - max(cas_latency_time, + MAX(cas_latency_time, timebase * info-> spd[channel][slot][CAS_LATENCY_TIME]); @@ -865,7 +865,7 @@ if (info->revision_flag_1) some_delay_2_ps = halfcycle_ps(info) >> 6; some_delay_2_ps += - max(some_delay_1_ps - 30, + MAX(some_delay_1_ps - 30, 2 * halfcycle_ps(info) * (some_delay_1_cycle_ceil - 1) + 1000) + 375; some_delay_3_ps = @@ -977,8 +977,8 @@ clock_speed_index]; } } - min_of_unk_2 = min(min_of_unk_2, a); - min_of_unk_2 = min(min_of_unk_2, b); + min_of_unk_2 = MIN(min_of_unk_2, a); + min_of_unk_2 = MIN(min_of_unk_2, b); if (rank == 0) { sum += a; count++; @@ -993,7 +993,7 @@ clock_speed_index]; if (unk1 >= t) max_of_unk = - max(max_of_unk, + MAX(max_of_unk, unk1 - t); } } @@ -1005,7 +1005,7 @@ [channel]] [info->clock_speed_index] + min_of_unk_2; if (unk1 >= t) - max_of_unk = max(max_of_unk, unk1 - t); + max_of_unk = MAX(max_of_unk, unk1 - t); } }
@@ -1177,7 +1177,7 @@ info->total_memory_mb = total_mb[0] + total_mb[1];
info->interleaved_part_mb = - pre_jedec ? 0 : 2 * min(total_mb[0], total_mb[1]); + pre_jedec ? 0 : 2 * MIN(total_mb[0], total_mb[1]); info->non_interleaved_part_mb = total_mb[0] + total_mb[1] - info->interleaved_part_mb; channel_0_non_interleaved = total_mb[0] - info->interleaved_part_mb / 2; @@ -1247,7 +1247,7 @@ halfcycle_ps(info) + 2230); some_delay_3_half_cycles = - min((some_delay_2_half_cycles + + MIN((some_delay_2_half_cycles + (frequency_11(info) * 2) * (28 - some_delay_2_half_cycles) / (frequency_11(info) * 2 - @@ -1351,7 +1351,7 @@
program_modules_memory_map(info, 1);
- MCHBAR16(0x610) = (min(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) + MCHBAR16(0x610) = (MIN(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) | (MCHBAR16(0x610) & 0x1C3) | 0x3C; MCHBAR16_OR(0x612, 0x100); MCHBAR16_OR(0x214, 0x3E00); @@ -1421,12 +1421,12 @@ if (TOM == 4096) TOM = 4032; TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64); - TOLUD = ALIGN_DOWN(min(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) + TOLUD = ALIGN_DOWN(MIN(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) , TOUUD), 64); memory_remap = 0; if (TOUUD - TOLUD > 64) { memory_remap = 1; - REMAPbase = max(4096, TOUUD); + REMAPbase = MAX(4096, TOUUD); TOUUD = TOUUD - TOLUD + 4096; } if (TOUUD > 4096) @@ -1472,7 +1472,7 @@ memory_map[0] = ALIGN_DOWN(uma_base_gtt, 64) | 1; memory_map[1] = 4096; for (i = 0; i < ARRAY_SIZE(memory_map); i++) { - current_limit = max(current_limit, memory_map[i] & ~1); + current_limit = MAX(current_limit, memory_map[i] & ~1); pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80, (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2); @@ -2737,9 +2737,9 @@ upper_margin = timings[center_178][channel][slot][rank][lane].largest - result; if (upper_margin < 10 && lower_margin > 10) - result -= min(lower_margin - 10, 10 - upper_margin); + result -= MIN(lower_margin - 10, 10 - upper_margin); if (upper_margin > 10 && lower_margin < 10) - result += min(upper_margin - 10, 10 - lower_margin); + result += MIN(upper_margin - 10, 10 - lower_margin); return result; }
@@ -3258,8 +3258,8 @@ g = gcd(freq1, freq2); freq1_reduced = freq1 / g; freq2_reduced = freq2 / g; - freq_min_reduced = min(freq1_reduced, freq2_reduced); - freq_max_reduced = max(freq1_reduced, freq2_reduced); + freq_min_reduced = MIN(freq1_reduced, freq2_reduced); + freq_max_reduced = MAX(freq1_reduced, freq2_reduced);
common_time_unit_ps = div_roundup(900000, lcm(freq1, freq2)); freq3 = div_roundup(num_cycles_2, common_time_unit_ps) - 1; @@ -3347,7 +3347,7 @@ 0, 1, &vv);
multiplier = - div_roundup(max + div_roundup(MAX (div_roundup(num_cycles_2, vv.common_time_unit_ps) + div_roundup(num_cycles_3, vv.common_time_unit_ps), div_roundup(num_cycles_1, @@ -3527,7 +3527,7 @@ for (rank = 0; rank < NUM_RANKS; rank++) if (info->populated_ranks[channel][slot][rank]) for (lane = 0; lane < 8 + info->use_ecc; lane++) - ret = max(ret, read_500(info, channel, + ret = MAX(ret, read_500(info, channel, get_timing_register_addr (lane, 0, slot, rank), 9)); diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 1a55d01..accafeb 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -14,8 +14,8 @@ */
#include <cbmem.h> +#include <commonlib/helpers.h> #include <stddef.h> -#include <stdlib.h> #include <symbols.h> #include <soc/emi.h>
@@ -23,5 +23,5 @@
void *cbmem_top_chipset(void) { - return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index a22d7e2..492238a 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -308,7 +308,7 @@ int matches = 0, sum = 0;
/* fine tune range from 0 to 127 */ - fine_val = min(max(fine_val, 0 - delta[0]), 127 - delta[6]); + fine_val = MIN(MAX(fine_val, 0 - delta[0]), 127 - delta[6]);
/* test gw fine tune */ for (i = 0; i < ARRAY_SIZE(delta); i++) { @@ -443,7 +443,7 @@
if (is_dual_rank(channel, sdram_params)) { /* RANKINCTL_ROOT1 = DQSINCTL + reg_TX_DLY_DQSGATE */ - value = min(opt_gw_coarse_value[channel][0], + value = MIN(opt_gw_coarse_value[channel][0], opt_gw_coarse_value[channel][1]) >> 2;
clrsetbits32(&ch[channel].ao_regs->dummy, 0xf, value); diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 6e3aabb..ccaa624 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -14,13 +14,13 @@ */
#include <cbmem.h> +#include <commonlib/helpers.h> #include <soc/addressmap.h> #include <soc/sdram.h> -#include <stdlib.h> #include <symbols.h>
void *cbmem_top_chipset(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index a7de16c..b6b568d 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -14,13 +14,13 @@ */
#include <cbmem.h> +#include <commonlib/helpers.h> #include <soc/addressmap.h> #include <soc/sdram.h> -#include <stdlib.h> #include <symbols.h>
void *cbmem_top_chipset(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); }
-
HAOUAS Elyes (Code Review) -
Kyösti Mälkki (Code Review)
-
Patrick Georgi (Code Review)