Change in coreboot[master]: soc/amd/common/espi_util: make decode enable parameter uint32_t

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44349 )

Change subject: soc/amd/common/espi_util: make decode enable parameter uint32_t
......................................................................

soc/amd/common/espi_util: make decode enable parameter uint32_t

Since this is a bit mask applied to the raw value of a 32 bit register,
this should be a 32 bit unsigned type.

Change-Id: I9d9930963d8c827a84dc1f67e2f2fa8f95ab40f2
Signed-off-by: Felix Held 
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44349/1

diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index ae5edb6..ba633a9 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -54,7 +54,7 @@
    write8((void *)(espi_get_bar() + reg), val);
 }

-static void espi_enable_decode(int decode_en)
+static void espi_enable_decode(uint32_t decode_en)
 {
    uint32_t val;

@@ -63,7 +63,7 @@
    espi_write32(ESPI_DECODE, val);
 }

-static bool espi_is_decode_enabled(int decode)
+static bool espi_is_decode_enabled(uint32_t decode)
 {
    uint32_t val;

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44349 )

Change subject: soc/amd/common/espi_util: make decode enable parameter uint32_t
......................................................................

Patch Set 1: Code-Review+2

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44349 )

Change subject: soc/amd/common/espi_util: make decode enable parameter uint32_t
......................................................................

soc/amd/common/espi_util: make decode enable parameter uint32_t

Since this is a bit mask applied to the raw value of a 32 bit register,
this should be a 32 bit unsigned type.

Change-Id: I9d9930963d8c827a84dc1f67e2f2fa8f95ab40f2
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44349
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index ae5edb6..ba633a9 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -54,7 +54,7 @@
    write8((void *)(espi_get_bar() + reg), val);
 }

-static void espi_enable_decode(int decode_en)
+static void espi_enable_decode(uint32_t decode_en)
 {
    uint32_t val;

@@ -63,7 +63,7 @@
    espi_write32(ESPI_DECODE, val);
 }

-static bool espi_is_decode_enabled(int decode)
+static bool espi_is_decode_enabled(uint32_t decode)
 {
    uint32_t val;