Change in coreboot[master]: mb/google/dedede: Update the sleep assertion widths and Power Cycle D...

[V Sowmya (Code Review)]

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the sleep assertion widths and Power Cycle Duration
......................................................................

mb/google/dedede: Update the sleep assertion widths and Power Cycle Duration

This patch updates the SLP_X assertion width and Power Cycle Duration
for the dedede platforms.

BUG=b:159104150

Change-Id: I7079cbd564288b5d5b69e07661434439365063d3
Signed-off-by: V Sowmya 
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/43792/1

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 7502489..27a3214 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -166,6 +166,20 @@
    # Skip the CPU repalcement check
    register "SkipCpuReplacementCheck" = "1"

+	/* Set the minimum assertion width */
+	register "PchPmSlpS3MinAssert"  = "3"  # 50ms
+	register "PchPmSlpS4MinAssert"  = "1"  # 1s
+	register "PchPmSlpSusMinAssert" = "3"  # 1s
+	register "PchPmSlpAMinAssert"   = "3"  # 98ms
+
+	# NOTE: Duration programmed in the below register should never be smaller than the
+	# stretch duration programmed in the following registers -
+	#       - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
+	#       - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
+	#       - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
+	#       - PM_CFG.SLP_LAN_MIN_ASST_WDTH
+	register "PchPmPwrCycDur" = "1"       # 1s
+
    device domain 0 on
    	device pci 00.0 on end # Host Bridge
    	device pci 02.0 on end # Integrated Graphics Device

[V Sowmya (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Jamie Chen, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Krishna P Bhat D, Aamir Bohra, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43792

to look at the new patch set (#2).

Change subject: mb/google/dedede: Update the sleep assertion widths and Power Cycle Duration
......................................................................

mb/google/dedede: Update the sleep assertion widths and Power Cycle Duration

This patch updates the SLP_X assertion width and Power Cycle Duration
for the dedede platforms.

BUG=b:159104150

Change-Id: I7079cbd564288b5d5b69e07661434439365063d3
Signed-off-by: V Sowmya 
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/43792/2

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the sleep assertion widths and Power Cycle Duration
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43792/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43792/3//COMMIT_MSG@7 
PS3, Line 7: sleep assertion widths
nit: sleep signal assertion widths

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the sleep assertion widths and Power Cycle Duration
......................................................................

Patch Set 3: Code-Review+2

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the sleep assertion widths and Power Cycle Duration
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/43792/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43792/3//COMMIT_MSG@7 
PS3, Line 7: Power Cycle Duration
power cycle duration

https://review.coreboot.org/c/coreboot/+/43792/3//COMMIT_MSG@9 
PS3, Line 9: SLP_X 
SLP_Sx

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[V Sowmya (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Jamie Chen, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Krishna P Bhat D, Aamir Bohra, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43792

to look at the new patch set (#4).

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

This patch updates the SLP_Sx assertion width and power cycle duration
for the dedede platforms.

Power cycle duration:
With default value,
    S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0

With value set to 1,
    S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0

BUG=b:159104150
TEST=Verified it on waddledoo.

Change-Id: I7079cbd564288b5d5b69e07661434439365063d3
Signed-off-by: V Sowmya 
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/43792/4

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 4:

(3 comments)

https://review.coreboot.org/c/coreboot/+/43792/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43792/3//COMMIT_MSG@7 
PS3, Line 7: Power Cycle Duration
> power cycle duration

Done

https://review.coreboot.org/c/coreboot/+/43792/3//COMMIT_MSG@7 
PS3, Line 7: sleep assertion widths
> nit: sleep signal assertion widths

Done

https://review.coreboot.org/c/coreboot/+/43792/3//COMMIT_MSG@9 
PS3, Line 9: SLP_X
> SLP_Sx

Done

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 4: Code-Review+2

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43792/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43792/4//COMMIT_MSG@20 
PS4, Line 20: Verified it on waddledoo.
test description pls.

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 4: Code-Review+1

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[V Sowmya (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Jamie Chen, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Krishna P Bhat D, Aamir Bohra, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43792

to look at the new patch set (#5).

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

This patch updates the SLP_Sx assertion width and power cycle duration
for the dedede platforms.

Power cycle duration:
With default value,
    S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0

With value set to 1,
    S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0

BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
     reset on waddledoo.

Change-Id: I7079cbd564288b5d5b69e07661434439365063d3
Signed-off-by: V Sowmya 
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/43792/5

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43792/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43792/4//COMMIT_MSG@20 
PS4, Line 20: Verified it on waddledoo.
> test description pls.

Done

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 5: Code-Review+1

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[Ronak Kanabar (Code Review)]

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43792 )

Change subject: mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur
......................................................................

mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur

This patch updates the SLP_Sx assertion width and power cycle duration
for the dedede platforms.

Power cycle duration:
With default value,
    S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0

With value set to 1,
    S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0

BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
     reset on waddledoo.

Change-Id: I7079cbd564288b5d5b69e07661434439365063d3
Signed-off-by: V Sowmya 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43792
Tested-by: build bot (Jenkins) 
Reviewed-by: Aamir Bohra 
Reviewed-by: Sridhar Siricilla 
Reviewed-by: Maulik V Vaghela 
Reviewed-by: Ronak Kanabar 
Reviewed-by: Subrata Banik 
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Aamir Bohra: Looks good to me, approved
  Maulik V Vaghela: Looks good to me, approved
  Ronak Kanabar: Looks good to me, approved
  Sridhar Siricilla: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index d0609ef..e7c5656 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -166,6 +166,20 @@
    # Skip the CPU repalcement check
    register "SkipCpuReplacementCheck" = "1"

+	# Set the minimum assertion width
+	register "PchPmSlpS3MinAssert"  = "3"  # 50ms
+	register "PchPmSlpS4MinAssert"  = "1"  # 1s
+	register "PchPmSlpSusMinAssert" = "3"  # 1s
+	register "PchPmSlpAMinAssert"   = "3"  # 98ms
+
+	# NOTE: Duration programmed in the below register should never be smaller than the
+	# stretch duration programmed in the following registers -
+	#       - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
+	#       - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
+	#       - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
+	#       - PM_CFG.SLP_LAN_MIN_ASST_WDTH
+	register "PchPmPwrCycDur" = "1"       # 1s
+
    device domain 0 on
    	device pci 00.0 on end # Host Bridge
    	device pci 02.0 on end # Integrated Graphics Device