Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31028
Change subject: mb/google/sarien: Replace B0D4 with TCPU ......................................................................
mb/google/sarien: Replace B0D4 with TCPU
Replace B0D4 with TCPU for DPTF thermal sensor. This helps to maintain consistency between coreboot and UEFI BIOS.
Change-Id: I024068c19160e1c08badef3d304ada14455c045f Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl 2 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/31028/1
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index fcc8798..f54a7c1 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -39,16 +39,16 @@
Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on Skin (TSR0) */ - Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
/* CPU Throttle Effect on DDR (TSR1) */ - Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR2) */ - Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, })
Name (MPPC, Package () diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index 459fb67..d6a1274 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -39,16 +39,16 @@
Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on Skin (TSR0) */ - Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
/* CPU Throttle Effect on DDR (TSR1) */ - Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR2) */ - Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, })
Name (MPPC, Package ()
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31028 )
Change subject: mb/google/sarien: Replace B0D4 with TCPU ......................................................................
Patch Set 2: Code-Review+2
You will probably need to rebase
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31028 )
Change subject: mb/google/sarien: Replace B0D4 with TCPU ......................................................................
mb/google/sarien: Replace B0D4 with TCPU
Replace B0D4 with TCPU for DPTF thermal sensor. This helps to maintain consistency between coreboot and UEFI BIOS.
Change-Id: I024068c19160e1c08badef3d304ada14455c045f Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/31028 Reviewed-by: Duncan Laurie dlaurie@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl 2 files changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index fcc8798..f54a7c1 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -39,16 +39,16 @@
Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on Skin (TSR0) */ - Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
/* CPU Throttle Effect on DDR (TSR1) */ - Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR2) */ - Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, })
Name (MPPC, Package () diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index 459fb67..d6a1274 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -39,16 +39,16 @@
Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on Skin (TSR0) */ - Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
/* CPU Throttle Effect on DDR (TSR1) */ - Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR2) */ - Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, })
Name (MPPC, Package ()
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Duncan Laurie (Code Review) -
Sumeet R Pawnikar (Code Review)