Change in coreboot[master]: soc/intel/baytrail,braswell: Sync PCI memory region in ASL

Show replies by date

1394
days inactive
1394
days old

coreboot-gerrit@coreboot.org

0 comments
1 participants

Add to favorites Remove from favorites

tags (0)
participants (1)
  • Kyösti Mälkki (Code Review)