Attention is currently required from: Sean Rhodes. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 )
Change subject: src/mainboard: Add Star Labs labtop series ......................................................................
Patch Set 6: Code-Review+1
(10 comments)
Patchset:
PS6: Suggestion: If you're willing, add yourself into the MAINTAINERS file with an entry for the StarLabs mainboards
Overall, looks pretty good, thanks Sean!
File Documentation/distributions.md:
https://review.coreboot.org/c/coreboot/+/55128/comment/79ab6c1e_a9b4b2eb PS6, Line 11: ### Purism : : [Purism](https://www.puri.sm) sells laptops with a focus on user privacy and : security; part of that effort is to minimize the amount of proprietary and/or : binary code. Their laptops ship with a blob-free OS and coreboot firmware : with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload. Does this belong with this commit?
File src/mainboard/starlabs/labtop/Kconfig:
https://review.coreboot.org/c/coreboot/+/55128/comment/87c34482_f2d62faa PS6, Line 26: # select HAVE_IFD_BIN : # select HAVE_ME_BIN Why commented out?
https://review.coreboot.org/c/coreboot/+/55128/comment/b2c72cb8_d735b266 PS6, Line 89: : config IFD_BIN_PATH : string : default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/$(CONFIG_VARIANT_DIR)/flashregion_0_flashdescriptor.bin" you have HAVE_IFD_BIN commented out, so this doesn't apply
https://review.coreboot.org/c/coreboot/+/55128/comment/aedd7d32_fbccb74a PS6, Line 94: config ME_BIN_PATH : string : default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/$(CONFIG_VARIANT_DIR)/flashregion_2_intel_me.bin" You have HAVE_ME_BIN commented out, so this doesn't apply
https://review.coreboot.org/c/coreboot/+/55128/comment/d0e12492_ce866a04 PS6, Line 112: #config VGA_BIOS_FILE : # string : # default "pci8086,9b41.rom" if BOARD_STARLABS_LABTOP_CML : # default "pci8086,5917.rom" if BOARD_STARLABS_LABTOP_KBL leave this out instead of commented out?
File src/mainboard/starlabs/labtop/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/55128/comment/5e9f1daa_4c4f6253 PS6, Line 54: space
File src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex:
PS6: Just curious, have you looked into util/spd_tools/ddr4?
File src/mainboard/starlabs/labtop/variants/cml/romstage.c:
https://review.coreboot.org/c/coreboot/+/55128/comment/95c61a6b_a9ded5c3 PS6, Line 41: (gpio_get(GPP_H6) < 2) | (gpio_get(GPP_E23) < 1) | gpio_get(GPP_E22); suggestion: use `gpio_base2_value` function, e.g.: ``` gpio_t memid_gpios[] = { GPP_E22, GPP_E23, GPP_H6 }; return (u8)gpio_base2_value(memid_gpios, ARRAY_SIZE(memid_gpios)); ```
Also I think you mean `gpio_get(GPP_H6) << 2` etc., not `gpio_get(GPP_H6) < 2`
File src/mainboard/starlabs/labtop/variants/kbl/romstage.c:
https://review.coreboot.org/c/coreboot/+/55128/comment/7c1dc5cc_e4099eca PS6, Line 26: /* struct region_device spd_rdev; */ remove