Change in coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock - coreboot-gerrit

5 Apr 2018


      build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25442 )
Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
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Patch Set 2:
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Gerrit-Change-Number: 25442
Gerrit-PatchSet: 2
Gerrit-Owner: Julien Viard de Galbert jviarddegalbert@online.net
Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Thu, 05 Apr 2018 10:00:22 +0000
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