Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37426 )

Change subject: soc/intel/tigerlake: Update Kconfig
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Patch Set 8:

(4 comments)

https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kco... 
File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kco... 
PS8, Line 84: 0x30000
> This CL conflicts with https://review.coreboot.org/c/coreboot/+/37764/. […]

+1 to Furquan's comments.

https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kco... 
PS8, Line 147: 7
> Is this really correct?

As per JSL EDS only 3 SPI ports

https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kco... 
PS8, Line 151: 8
> I see only 6 in EDS.

As per JSL EDS only 6 I2C ports

https://review.coreboot.org/c/coreboot/+/37426/8/src/soc/intel/tigerlake/Kco... 
PS8, Line 155: 	default 7
As per JSL EDS only 3 UART ports