Patch set updated for coreboot: a9fcd41 intel/fsp_baytrail: Add padding so device_nvs location matches ACPI

[Scott Radcliffe]

Scott Radcliffe ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7038

-gerrit

commit a9fcd4167cac99412ec9c373f29ddf6b648a7e9b
Author: Scott Radcliffe 
Date:   Fri Oct 10 16:09:52 2014 -0400

intel/fsp_baytrail: Add padding so device_nvs location matches ACPI

The offset of the device_nvs in the gnvs struct is expected to be
    0x1000. It is actually 0x100 so padding is needed to move device_nvs
    to the expected location. ACPI references to device_nvs objects will
    be correct with the padding.

This was tested using a Micro Industries customized Baytrail-I board
    based on the Intel Bayley Bay CRB. In intel/baytrail/nvs.h, there's
    a Google customized structure located at 0x0100-0x0FFF that is
    removed from the fsp_baytrail/nvs.h which explains the mismatch here.

Change-Id: I4721a79b53b5b3345ff9b0c053bdd31d2cf9cb61
    Signed-off-by: Scott Radcliffe 
---
 src/soc/intel/fsp_baytrail/baytrail/nvs.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/fsp_baytrail/baytrail/nvs.h b/src/soc/intel/fsp_baytrail/baytrail/nvs.h
index 53c4a64..242f6d3 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/nvs.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/nvs.h
@@ -61,6 +61,9 @@ typedef struct {
    u32	cbmc; /* 0x38 - coreboot memconsole */
    u8	rsvd3[196];

+	/* Pad 0x0100-0x0fff */
+	u8	rsvd4[3840];
+
    /* Baytrail LPSS (0x1000) */
    device_nvs_t dev;
 } __attribute__((packed)) global_nvs_t;