Change in ...coreboot[master]: mb/google/hatch: Enable NVME support for Hatch

[V Sowmya (Code Review)]

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30431

Change subject: mb/google/hatch: Enable NVME support for Hatch
......................................................................

mb/google/hatch: Enable NVME support for Hatch

This patch enables the x4 NVME device for hatch,
* Enable the Root port 9.
* Assign the usage type for clock source.
* Configure the GPIO for CLK SRC 1.

Change-Id: I69be6b21a5ae5962877a5c38180b5ffac532fed4
Signed-off-by: V Sowmya 
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/gpio.c
2 files changed, 11 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30431/1

diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 3cdc3e0..ff48b54 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -40,6 +40,14 @@
    register "InternalGfx" = "1"
    register "SkipExtGfxScan" = "1"

+	# Enable Root port 9(x4) for NVMe.
+	# Enable CLKREQ#
+	register "PcieRpEnable[8]" = "1"
+	# RP 9 uses CLK SRC 1
+	register "PcieClkSrcUsage[1]" = "8"
+	# ClkReq-to-ClkSrc mapping for CLK SRC 1
+	register "PcieClkSrcClkReq[1]" = "1"
+
    device domain 0 on
    	device pci 00.0 off end # Host Bridge
    	device pci 02.0 on  end # Integrated Graphics Device
@@ -80,7 +88,7 @@
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
    	device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 off end # PCI Express Port 9
+		device pci 1d.0 on  end # PCI Express Port 9 (X4 NVME)
    	device pci 1d.1 off end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index 489c489..ba7f734 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -21,6 +21,8 @@
 static const struct pad_config gpio_table[] = {
    /* TRACKPAD_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT),
+	/* SRCCLKREQ1 */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
    /* H1_SLAVE_SPI_CS_L */
    PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
    /* H1_SLAVE_SPI_CLK */